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The impact of a 60 MeV proton irradiation on the drain induced barrier lowering is investigated for tri-gate FinFETs processed with and without the implementation of different biaxial or uniaxial strain engineering techniques. A contrasting behavior is observed for n- and pFinFETs, which may be associated with the radiation-induced charges in the buried oxide and the influence of the back channel...
A novel methodology to statistically analyze the statistics on small device performance is presented for the first time. To verify the accuracy of analysis and modeling, TCAD simulation is used to mimic possible process-induced and random fluctuations. The proposed approach precisely decouples various process dependency of the device electric behavior and predicts the device performance trend induced...
This paper reports modeling the parasitic bipolar device in the 40 nm PD SOI NMOS device considering the floating body effect. Using a unique extraction method, the function of the parasitic bipolar device during transient operations could be modeled. During the turn-on transient by imposing a step voltage from 0 V to 2 V at the gate, the case with a slower rise time shows a faster turn-on in the...
A non-trivial nature of the power management circuit design is emphasized based on three case studies. The events of transient latchup and device failure under Charged Device Model (CDM) pulse due to an unexpected current path in power analog circuits are analyzed demonstrating the value of mixed-mode simulation approach.
We report a bias dependent body resistance model for deep submicron PDSOI technology. This model is well verified by the measured data based on the 0.35μm PDSOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS), and can be implemented in the SOI MOSFET compact model like BISMSOI.
In this paper, we present an improved charge pump circuit for the non-volatile memories in RFID tags. The circuit consists of a single pumping branch without auxiliary capacitors and operates with a simple two-phase clock. The internal high voltages are used to control the gate and bulk terminals of the charge transfer switch. As a result, the threshold voltage loss and the leakage currents are eliminated...
In this article, an optimized transient performance CCL-LDO is proposed, which adopts the controlling method of the charge pump phase-locked loop. With 1μF decoupling capacitor, the experimental results based on 0.13μm CMOS process show that the output voltage is 1.0V, and when the workload changes from 100μA to 100mA transiently, the stable dropout is 4.25mV, settling time is 8.2μs and undershoot...
Because of the special p-i-n structure of the tunneling FET (TFET), many different composite transistors can be formed with careful device design by combining TFET with MOSFET. In this paper, we propose the special applications of TFET as memory devices. A novel capacitor-less DRAM cell based on floating junction gate (FJG) concept can be configured with TFET. In addition, several different memory...
The memory effect in floating nanodot gate field effect transistor (FET) was investigated by fabricating biomineralized inorganic nanodot embedded metal-oxide-semiconductor (MOS) devices. Artificially biomineralized Co oxide cores accommodated in ferritins were utilized as a charge storage node of floating gate memory. Two dimensional array of Co oxide core accommodated ferritin were, after selective...
Graphene, a two-dimensional carbon form with the highest intrinsic carrier mobility and many desirable physical properties at room temperature, is considered a promising material for ultrahigh speed and low power devices with the possibility of strong scaling potential due to the ultra-thin body. (Fig. 1) [1-3] Here IBM reports progress in graphene nanoelectronics, synthesizing wafer-scale monolayer-controlled...
In this study, we propose a new technology to fabricate pseudo tri-gate vertical (PTGV) MOSFETs without p-n junctions, named junctionless PTGVMOS (JPTGV). According to numerical analysis, the excellent electrical characteristics such as subthreshold swing (S.S.) ~ 60mV/dec, Ion/Ioff ~ 1010, and low interface trap density are all achieved. The device without p-n junctions provides an easier way for...
This work presents a preliminary performance comparison between the new and conventional block oxide (BO) bulk-MOSFETs that suggests the proposed BO structure as a candidate for scaling planar CMOS to 16 nm generation and beyond. Also, the combined application of the isolation-last process (ILP) and the BO process provides a method of forming a new BO (NBO) structure that diminishes the short-channel...
In this work, we studied current transport in mono-, bi-and tri-layer graphene. We find that both the temperature and carrier density dependencies in monolayer and bi-/tri-layers are diametrically opposite. These difference can be understood by the different density-of-states and the additional screening of the electrical field of the substrate surface polar phonons in bi-layer/tri-layer graphenes...
In this study, the electrical characteristics of high-k Tb2O3 polyoxide capacitors combined with rapid thermal post annealing have been improved (i.e.lower leakage current, higher electrical breakdown filed and lower electron trapping rate). The post-RTA annealing treatment can passivate and reduce trap states to terminate dangling bonds and traps in the high-k Tb2O3 dielectric and the interface between...
La2O3 insulators have been prepared by ALD using La(iPrCp)3 and H2O as the source materials. We identified two necessary conditions to achieve the self-limiting growth: temperatures lower than 200°C and extremely long purging after H2O pulses. La2O3 insulators annealed at 500°C showed good MOS properties with no hysteresis and small flat-band voltage shift. Comparisons to the have La2O3 films prepared...
Silicon nanowire transistor with side-gate and back-gate has been fabricated by electron beam lithography combined with dry oxidation on a doped silicon-on-insulator wafer. The effects of back-gate and side-gate on the properties of single electron transport were investigated by measuring the channel current as function of the applied gate voltages. The tunable single electron effect and Coulomb oscillations...
An overview of metallic source/drain (MSD) contacts in nanoscaled MOSFET technology is provided in this paper. MSD contacts offer several benefits for nanoscaled CMOS, i.e., extremely low S/D parasitic resistance, abruptly sharp junctions between S/D and channel and preferably low temperature processing. In order to achieve high performance MSD MOSFETs, many design parameters such as Schottky barrier...
The review addresses the major challenges that Nanoelectronics will have to face in the next decades. A multifaced strategy is followed to scale down CMOS based technology with new materials and disruptive architectures, heterogeneous integration, alternatives to MOSFET for information processing introducing 3D schemes at the Front End and back end levels.
We successfully achieved the reduction of the parasitic resistance and the mobility enhancement in Si nanowire transistors (NW Tr.) by raised source/drain extensions with thin spacer (<;10nm) and by stress induced from heavily-doped gate. Id variations are suppressed by the spacer thinning. By adopting <;100> NW channel instead of <;110> NW, Ion = 1 mA/μm for Ioff = 100 nA/μm is achieved...
A current buffer compensation Low Dropout (LDO) regulator for portable applications is present in this paper. The current buffer compensation scheme is a current feedback amplifier, which provides low output impendence in order to move the non-dominant pole due to the large gate capacitance of the pass transistor of the LDO regulator to high frequency. This LDO circuit had been designed and implemented...
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