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The review addresses the major challenges that Nanoelectronics will have to face in the next decades. A multifaced strategy is followed to scale down CMOS based technology with new materials and disruptive architectures, heterogeneous integration, alternatives to MOSFET for information processing introducing 3D schemes at the Front End and back end levels.
We successfully achieved the reduction of the parasitic resistance and the mobility enhancement in Si nanowire transistors (NW Tr.) by raised source/drain extensions with thin spacer (<;10nm) and by stress induced from heavily-doped gate. Id variations are suppressed by the spacer thinning. By adopting <;100> NW channel instead of <;110> NW, Ion = 1 mA/μm for Ioff = 100 nA/μm is achieved...
Strain has been introduced into the channel region of metal-oxide-semiconductor (MOS) field-effect transistor to improve its operating speed in modern integrated circuits (IC). In this work, we investigated the influence of uniaxial compressive and tensile strains on the nanoscale electrical characteristics of thin gate silicon dioxide (SiO2) films. Both the nanoscale I-V characteristics and cumulative...
An improved 4H-SiC MESFETs with varied p-buffer layer thickness is proposed, and the static and dynamic electrical performances are analyzed in this paper. The variation in p-buffer layer depth leads to the change in the active channel thickness and modulates the electric field distribution inside the channel. Detailed numerical simulations demonstrate that the saturation drain current and the maximum...
We have investigated the role of oxygen in Hf-based high-k gate stacks on Vfb shift. It is clearly shown that the Vfb of the HfSiOx-based high-k materials of the weak ionic oxide was almost constant irrespective of the oxidation annealing temperature. On the other hand, the HfO2-based high-k materials of the strong ionic oxide caused the positive Vfb shifts by introducing additional oxygen into high-k...
The edge field enhanced deep depletion phenomenon in metal-oxide-semiconductor (MOS) structure was demonstrated. The analysis in inversion to deep depletion of ultra-thin SiO2 and HfO2 was conducted using critical field model. By examine the field ratio between edge and bulk, it is observed that the HfO2 has larger ratio than SiO2. It is supposed the edge field enhanced deep depletion phenomenon dominates...
A novel structure of 4H-SiC MESFETs is proposed which focuses on surface trap suppression. A MOS gate controlled spacer layer is shown to improve both DC and AC characteristics due to suppressed surface effect and decreased gate capacitance. A very high power density of 6.1 W/mm is obtained at S band operation. Compare with the well recognized buried gate structure, there is a significant improvement...
TaN was widely used as Cu diffusion barrier in CMOS Cu-BEOL technology, in which it was removed by CMP process. Some work was done on TaN etch by Br/Cl-based gas for metal gate application. But seldom work was done for TaN etch in CF-based gas. In this work TaN etching in CF4/CHF3 gas was investigated on CVD alpha-Si substrate for CMOS compatible MEMS/Sensor application. To avoid resist poisoning...
Degradation of electrical characteristics of NdAlO3/SiO2 stack gate under the constant voltage stress (CVS) is presented. It is found that the electron trapping, positive charges and oxide trap generation acts together, which causes the degradation of NdAlO3/SiO2 stack gate. The transport mechanisms of the gate leakage current in NdAlO3/SiO2 stack gate are also investigated. Frenkel-Poole emission...
Normalized Differential Conductance Spectroscopy (NDCS) has been used to investigate the tunneling properties of post soft breakdown SiO2. It is shown that the NDCS is capable of separating various components of tunneling current and determining its corresponding tunnel constants of post SBD SiO2. Therefore, the most important tunneling parameters: the effective mass of tunneling electron in SBD SiO...
Continuously down-scaling EOT and improving mobility are required for CMOS device. Small 0.6~1 nm EOT and low Vt of ~0.15 V are achieved in CMOS by using higher κ gate dielectric and novel process. The ultimate EOT scaling is limited by the inserted ultra-thin SiON interfacial layer in high-κ/Si to reduce the mobility degradation. Further mobility improvement is obtained by using Ge channel MOSFET...
A cell-based analytical percolation model recently proposed for the dielectric breakdown (BD) of high-K stack gate dielectrics is reformulated in terms of competing local percolation paths. The model is equivalent to kinetic Monte Carlo implementation of percolation and it is shown to be consistent with large sample size statistical data. This is a physics-based picture that predicts the scaling of...
In this paper, we discuss the research and development of several key process modules for realizing high-mobility III-V n-MOSFETs. Interface passivation technologies were developed to realize high quality gate stacks on III-V. InGaAs MOSFETs with in situ doped lattice-mismatched source/drain (S/D) stressors were demonstrated for reduction of S/D series resistance as well as channel strain engineering...
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