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A new two-step program scheme is proposed for Si nanocrystal memory devices. The new scheme combines one soft Fowler-Nordheim (FN) program at low voltage and one channel-hot-electron (CHE) program. The device characteristics are compared under cycling of FN erasing and three different program methods: FN program, CHE program and the new two-step program scheme. The new scheme not only gives a large...
PIN tunneling field effect transistor (TFET) is one of the most promising devices due to its low sub-threshold swing. In this paper, using TCAD simulation, we investigate the doping and structure dependence of the electric field in PIN TFET. We show that an insertion of a thin N layer into PIN structure (i.e., PNIN TFET) not only enhances the drive current but also improves the reliability of the...
Coulomb diamonds were clearly observed on single-electron transistors (SETs) fabricated by bottom-up processes of electroless plating of Au nanogap electrodes and chemisorption of a Au nanoparticle at 80 K. In the drain current-drain voltage characteristics, Coulomb staircases were modulated by the side gate voltage. Tunneling resistances and source/drain/gate capacitances of the SET were evaluated...
This work presents the mechanism of Stress induced leakage current (SILC) under NBT stress. Experiment results show that there are three kinds of oxide traps generated under NBT stress: hole traps with full recoverable characteristic, hydrogen related traps with irrecoverable characteristic and a kind of positive trap which can promote the hole tunneling after neutralization. The cause of SILC is...
The edge field enhanced deep depletion phenomenon in metal-oxide-semiconductor (MOS) structure was demonstrated. The analysis in inversion to deep depletion of ultra-thin SiO2 and HfO2 was conducted using critical field model. By examine the field ratio between edge and bulk, it is observed that the HfO2 has larger ratio than SiO2. It is supposed the edge field enhanced deep depletion phenomenon dominates...
This paper summarizes our recent investigations of nano-wire n type tunneling field effect transistor (n-TFET) reliability by experimental measurements and physical analysis [1-3]. Large PBTI and HC degradations which are very different from those in conventional n-MOSFETs were observed. The results are interpreted by different degradation mechanism in TFET.
Contradiction of threshold voltage shift window and endurance severely restricts the application of silicon nanocrystals (Si-NCs). Pre-cycling with higher program/erase (P/E) voltages greatly improves the endurance performance. Baked at 150°C, decreases of stored charges at programmed states have a similar trend, which proves the optimized method does not bring more traps than normal P/E cycling.
Degradation of electrical characteristics of NdAlO3/SiO2 stack gate under the constant voltage stress (CVS) is presented. It is found that the electron trapping, positive charges and oxide trap generation acts together, which causes the degradation of NdAlO3/SiO2 stack gate. The transport mechanisms of the gate leakage current in NdAlO3/SiO2 stack gate are also investigated. Frenkel-Poole emission...
Normalized Differential Conductance Spectroscopy (NDCS) has been used to investigate the tunneling properties of post soft breakdown SiO2. It is shown that the NDCS is capable of separating various components of tunneling current and determining its corresponding tunnel constants of post SBD SiO2. Therefore, the most important tunneling parameters: the effective mass of tunneling electron in SBD SiO...
An experimental method is proposed to extract the channel hot-electron (CHE) energy (φe) in the nano-meter-scaled metal-oxide-semiconductor field-effect transistors (MOSFETs). Accelerated by localized electric field in the drain induced channel depletion region, the CHEs obtain larger kinetic energy than the other unaccelerated channel electrons, and they gain greater probability of tunneling through...
The DC and analog/RF performance of p-channel Schottky barrier Si and Ge nanowire transistors are simulated and some impact factors are studied. The results suggest that 100meV and 50meV are the most optimized Schottky barrier height for intrinsic gain and cutoff frequency respectively. Thinner nanowires enhance the drivability of silicon devices while impair that of germanium devices. With gate length...
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