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We report a bias dependent body resistance model for deep submicron PDSOI technology. This model is well verified by the measured data based on the 0.35μm PDSOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS), and can be implemented in the SOI MOSFET compact model like BISMSOI.
The transient effect of graded channel partially-depleted silicon-on-insulator nMOSFETs are analyzed by SILVACO ATLAS software. The switch on and switch off transient behaviors are studied for the device. While the device operates in the kink region, the transient effects of drain current were also investigated. It was found that the transient characteristic of the graded channel device was superior...
A new planar-type body-connected FinFET structure produced by the isolation-last self-align process is demonstrated and characterized by using three-dimensional (3-D) numerical simulations. The new process step first defines the gate region and then the active region, thus it can achieve fully self-alignment undoubtedly. Besides, due to the isolation-last process (ILP), an additional body region (ABR)...
In this work, we study the impact of device self-heating on Bulk and double-gate silicon-on-insulator (DGSOI) technologies using self-consistent electrothermal (ET) simulations. Device characteristics of Bulk and DGSOI MOSFETs have been studied to estimate device performance and the impact of self-heating on the same. Self-heating effect (SHE) on the AC performance has also been studied for these...
The threshold voltage, Vth of a double-gate Schottky-Barrier (DGSB) source/drain (S/D) metal-oxide-semiconductor field-effect transistor (MOSFET) has been investigated. An analytic expression for surface potential in the channel is obtained and the results are verified via simulations, good agreement is observed. A new definition for Vth is given, and an analytic expression for Vth is presented. We...
In this paper, a short-channel subthreshold swing model for three-terminal (3T) double-gate (DG) MOSFETs with Gaussian doping profile in the vertical direction of the channel is presented. The effective conduction path effect concept of uniformly doped DG MOSFETs is utilized to incorporate the doping dependency in the present model. The effect of varying peak doping position of Gaussian profile on...
This paper presents a predictive electrostatic capacitance and resistance compact model of multiple gate MOSFET with cylindrical conducting channels, taking into account parasitic effects, quantum confinement and quasi-ballistic effects. The model incorporates the dependence of channel length, gate height and width, gate-to-contact spacing, nanowire size, multiple channels, as well as 1-D ultra-narrow...
The dual-material gate and asymmetrical halo structure is used in surrounding gate MOSFET to improve the performance. By treating the device as three surrounding-gate MOSFETs connecting in series and maintaining current continuity, a comprehensive drain current model is developed for it. It is concluded that the device also exhibits increased current drivability and improved hot carrier reliability...
A SPICE-compatible circuit model for multi-sensor CDPS SENSE-FET (Current Detection and Power Self-Supply Sense Field Effect Transistor) is proposed. Based on the discrepancy in the current flow-lines, the subcircuit model is developed by employing the piecewise model equivalence. A dual-gate controlling model has been included to precisely describe the controllable charging current. Simulations,...
Based on the exact solution of the Poisson's equation, a new two-dimensional (2-D) model for the silicon-on-insulator (SOI) fully-depleted four-gate transistor(G4-FET) is successfully developed. The model is verified by its good agreement with the numerical simulation of the device simulator. For the threshold voltage degradation, it is found that the lateral coupling effects between lateral gate...
In this paper, the influence of the different length of the drift region and the field plate upon Hot-Carrier-Induced on-resistance (Ron) and threshold voltage (Vth) degradation in p-type lateral extended drain MOS (pLEDMOS) transistor with thick gate oxide has been investigated. It was concluded that increasing the length of drift region can reduce the Ron degradation but enhance the Vth degradation...
This paper presents on-state characteristics of two types of UTB FD MOSFETs simulated by Monte Carlo method. The two devices under investigation have elevated and recessed source/drain respectively. The comparison of non-stationary transports effect is made between the two devices. Different non-stationary transports effect in the two devices is the cause of different on state characteristics. Transit...
An analytical model is presented for the 3D subthreshold electrostatics of low-doped gate-all-around MOSFETs with circular and square cross sections. The model is based on a solution of the 3D Laplace equation utilizing the high symmetry of the devices and assuming near-parabolic potential distributions in the directions perpendicular to the gates for the central regions. To account for short-channel...
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