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In this paper, we present an improved charge pump circuit for the non-volatile memories in RFID tags. The circuit consists of a single pumping branch without auxiliary capacitors and operates with a simple two-phase clock. The internal high voltages are used to control the gate and bulk terminals of the charge transfer switch. As a result, the threshold voltage loss and the leakage currents are eliminated...
In this article, an optimized transient performance CCL-LDO is proposed, which adopts the controlling method of the charge pump phase-locked loop. With 1μF decoupling capacitor, the experimental results based on 0.13μm CMOS process show that the output voltage is 1.0V, and when the workload changes from 100μA to 100mA transiently, the stable dropout is 4.25mV, settling time is 8.2μs and undershoot...
A fast integrated gate driver with amorphous silicon thin film transistor (a-Si:H TFT) is proposed in this paper. To improve the circuit speed, a new input scheme is designed to provide a full scale pre-charge voltage. So the loss of pre-charge voltage, a challenge in the conventional designs, is avoided. Simulations show that the proposed gate driver has a much improved driving speed in comparison...
In this paper, we report our approaches in realizing EOT of 0.5nm and below with rare earth La2O3 high-k gate dielectric. An EOT of 0.43nm was obtained from a TiN/W/La2O3(3nm)/n-Si capacitor by optimizing the thickness W layer. Our results show that a proper gate electrode is one of the most important factors for realizing EOT below 0.5nm.
A successive approximation register analog-to-digital converter(SAR ADC) targeted for use in RSSI(received signal strength indicator) is presented. The measured signal-to-noise-and-distortion ratios(SNDR) of the ADC is 53.95 dB at 1MS/s sampling rate with power consumption of 147.6 μW from 1.2-V supply voltage, thus the resulting FOM is 0.437 pJ/conversion-step. The ADC is fabricated in a 0.13-μm...
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