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This paper reports modeling the parasitic bipolar device in the 40 nm PD SOI NMOS device considering the floating body effect. Using a unique extraction method, the function of the parasitic bipolar device during transient operations could be modeled. During the turn-on transient by imposing a step voltage from 0 V to 2 V at the gate, the case with a slower rise time shows a faster turn-on in the...
Silicon nanowire transistor with side-gate and back-gate has been fabricated by electron beam lithography combined with dry oxidation on a doped silicon-on-insulator wafer. The effects of back-gate and side-gate on the properties of single electron transport were investigated by measuring the channel current as function of the applied gate voltages. The tunable single electron effect and Coulomb oscillations...
Analog circuit designs are often biased to work in sub-threshold mode with good gate-source voltage matching performances. Depending on the process, hump effect may change the MOS characteristics for negative Bulk-Source Voltage (VBS) and have a slight impact for VBS=0V. To model the hump effect, two narrow parasitic MOS are introduced in parallel with the main device. To accurately simulate matching...
The conventional threshold voltage shift measured by extrapolating transfer characteristics, ΔVth(ex), underestimates the NBTI-induced degradation of drain current, ΔId. Mobility degradation, Δμ, has been proposed as a potential contributor to ΔId. Evaluating Δμ, however, can be problematic and controversial. For test engineers, it is desirable to include all degradations in one parameter and we propose...
A new type of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with self-aligned metal electrodes (SAME) is systematically characterized. New device features different from conventional poly-Si TFTs are found, and are attributed to the presence of Schottky barriers at the channel ends.
Space applications using advanced foundry processes require accurate assessment of the dependence of total-ionizing dose (TID) response on process variability and layout. A new test chip is described to enable large sample of device measurements under irradiation. The variability of TID-induced leakage current and transistor mismatch both increase after irradiation.
A new procedure to determine source/drain series resistance and effective channel length has been developed for MOSFETs operated in linear region. The gate-bias dependence of source/drain resistance is considered by differential and integration processes. This new-developed procedure has been applied to devices with mask channel lengths of 0.23, 0.2, and 0.185 μm. The parameters extracted with this...
This work presents the mechanism of Stress induced leakage current (SILC) under NBT stress. Experiment results show that there are three kinds of oxide traps generated under NBT stress: hole traps with full recoverable characteristic, hydrogen related traps with irrecoverable characteristic and a kind of positive trap which can promote the hole tunneling after neutralization. The cause of SILC is...
A new structure of high-voltage junction FET was designed by using a 40 V LDMOS technology without additional mask in this process. This JFET also has the same breakdown capability as the LDMOSFET. The pinch-off voltage of the JFET was determined by layout, the n-well opening. The pinch-off voltage was almost unchanged with temperature variation. This JFET can be used in circuit applications with...
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