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We successfully achieved the reduction of the parasitic resistance and the mobility enhancement in Si nanowire transistors (NW Tr.) by raised source/drain extensions with thin spacer (<;10nm) and by stress induced from heavily-doped gate. Id variations are suppressed by the spacer thinning. By adopting <;100> NW channel instead of <;110> NW, Ion = 1 mA/μm for Ioff = 100 nA/μm is achieved...
Electron and hole mobility in sub-10nm silicon nanowire FETs on (100) SOI has been systematically investigated experimentally. The nanowire height of fabricated nanowire FETs is as low as 4 - 10nm and the minimum nanowire width is shrunk to 5nm. Higher hole mobility than (100) universal mobility is experimentally observed for the first time in 9nm-wide nanowire and even in 5nm-wide nanowire, while...
The electrical transport behavior of carbon nanotube field-effect transistors (CNT-FETs) decorated with gold nanoparticles (NPs) has been investigated. After decoration with Au NPs, the Ion/Ioff ratios of nanotube FETs decrease and some of the p-type devices even change into metallic ones. The Au NPs decrease the contact resistances between the CNTs and metal electrodes, and accordingly increase the...
In this work we report the main results of a research activity on a novel device concept which aims to achieve a steep switching behavior based on the filtering of high-energy electrons in the FET source region. The filtering function is entrusted to a superlattice in the source extension, which could possibly be fabricated by depositing a number of appropriate semiconductor layers within the manufacturing...
Modeling of resonant detection of terahertz (THz) radiation of Metal-Oxide-Semiconductor (MOS) field effect transistors (FETs) under the optical beating mode is studied in this paper. An analytical model is first proposed which covers all operation regions of FETs from sub-threshold to the strong inversion, and then is verified by the numerical tool which has been improved to simulate THz detection...
Silicon-germanium dots grown in the Stranski-Krastanow mode are investigated as sources of strain for electron mobility enhancement in the silicon capping layer. N-channel MOSFETs with the channel in the Si cap-layer over the SiGe dot (DotFETs) are fabricated in a custom-made process and have an average increase in drain current of up to 22.5% compared to the reference devices. The sources of device...
This paper describes 0.18um CMOS silicon-on-insulator (SOI) technology and design techniques for SOI RF switch designs for wireless applications. The measured results of SP4T (single pole four throw) and SP8T (single pole eight throw) switch reference designs are presented. It has been demonstrated that SOI RF switch performance, in terms of power handling, linearity, insertion loss and isolation,...
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