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In this paper, we present an improved charge pump circuit for the non-volatile memories in RFID tags. The circuit consists of a single pumping branch without auxiliary capacitors and operates with a simple two-phase clock. The internal high voltages are used to control the gate and bulk terminals of the charge transfer switch. As a result, the threshold voltage loss and the leakage currents are eliminated...
This paper presents a new poly-Si thin film transistor (TFT) pixel circuit for active-matrix organic light-emitting diode (AMOLED) displays. The pixel circuit has a simple four-transistor configuration and is controlled by two adjacent gate scan pulses, allowing a small circuit area and simple driving scheme. Simulation results show that this pixel circuit can provide the OLED with a current non-uniformity...
The conventional threshold voltage shift measured by extrapolating transfer characteristics, ΔVth(ex), underestimates the NBTI-induced degradation of drain current, ΔId. Mobility degradation, Δμ, has been proposed as a potential contributor to ΔId. Evaluating Δμ, however, can be problematic and controversial. For test engineers, it is desirable to include all degradations in one parameter and we propose...
The transient effect of graded channel partially-depleted silicon-on-insulator nMOSFETs are analyzed by SILVACO ATLAS software. The switch on and switch off transient behaviors are studied for the device. While the device operates in the kink region, the transient effects of drain current were also investigated. It was found that the transient characteristic of the graded channel device was superior...
High and random voltages are big challenges for practical applications of organic thin film transistors (OTFTs). Herein, a route to achieve devices with both low operating voltages (Vop) and tunable threshold voltages (VTH) was proposed. The Vop was reduced to be less 3 V without lowering the mobility and the ratio of on/off current using a 30 nm Al2O3 insulator film fabricated by atomic layer deposition...
The threshold voltage, Vth of a double-gate Schottky-Barrier (DGSB) source/drain (S/D) metal-oxide-semiconductor field-effect transistor (MOSFET) has been investigated. An analytic expression for surface potential in the channel is obtained and the results are verified via simulations, good agreement is observed. A new definition for Vth is given, and an analytic expression for Vth is presented. We...
In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic properties, source/drain series resistance (RSD), and driving current. The SDE-RDF induced variations of threshold voltage (Vth) and DIBL in SNWTs with different diameters are found to...
A new procedure to determine source/drain series resistance and effective channel length has been developed for MOSFETs operated in linear region. The gate-bias dependence of source/drain resistance is considered by differential and integration processes. This new-developed procedure has been applied to devices with mask channel lengths of 0.23, 0.2, and 0.185 μm. The parameters extracted with this...
Based on the exact solution of the Poisson's equation, a new two-dimensional (2-D) model for the silicon-on-insulator (SOI) fully-depleted four-gate transistor(G4-FET) is successfully developed. The model is verified by its good agreement with the numerical simulation of the device simulator. For the threshold voltage degradation, it is found that the lateral coupling effects between lateral gate...
This study presents a new buried-gate vertical MOSFET (BGVMOS) with suppressed overlap capacitance and improved electrical characteristics due to its modified gate structure. According to the TCAD simulations, our proposed BGVMOS structure can gain reduced parasitic capacitances (27.11% Cgd and 37.53% Cgs at VDs = 1.0 V), improved drain saturation current, and free kink effect, in comparison to a...
With the technology scaling down to the deep sub-micron domain, leakage power increases rapidly in VLSI, enhancing the area overhead of dynamic power management system. Reverse Body Bias(RBB) is a common method to reduce the leakage power at run-time. To overcome the larger area overhead of controller applied on RBB, this paper proposes a new way of connection, which can reduce area of controller...
Contradiction of threshold voltage shift window and endurance severely restricts the application of silicon nanocrystals (Si-NCs). Pre-cycling with higher program/erase (P/E) voltages greatly improves the endurance performance. Baked at 150°C, decreases of stored charges at programmed states have a similar trend, which proves the optimized method does not bring more traps than normal P/E cycling.
The Zero Temperature Coefficient (ZTC) is investigated experimentally in planar and standard/biaxially strained triple-gate nFinFETs fabricated on SOI wafers. In this work a simple model to analyze the behavior of the gate-source voltage at the Zero Temperature Coefficient point (VZTC) is proposed in the linear and saturation operation regions. The analysis takes into account the temperature variations...
The retention characteristics of Flash Memory structures was mainly studied using Proportional Difference Operator (PDO) method in this paper. This method makes it rapid to extract the leakage time constant of charge in floating gate.
We have investigated static variability of p-MOSFETs by evaluating the drain current under various conditions of gate and drain voltages. The value of drain current variability (σId/Id) is proportional to (LW)-1/2 before the short channel effect appears, being similar to that of Vt variability. The magnitude of σId/Id decreases as the gate overdrive (Vg-Vt) decreases and classified into two regimes...
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