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We successfully achieved the reduction of the parasitic resistance and the mobility enhancement in Si nanowire transistors (NW Tr.) by raised source/drain extensions with thin spacer (<;10nm) and by stress induced from heavily-doped gate. Id variations are suppressed by the spacer thinning. By adopting <;100> NW channel instead of <;110> NW, Ion = 1 mA/μm for Ioff = 100 nA/μm is achieved...
A fast integrated gate driver with amorphous silicon thin film transistor (a-Si:H TFT) is proposed in this paper. To improve the circuit speed, a new input scheme is designed to provide a full scale pre-charge voltage. So the loss of pre-charge voltage, a challenge in the conventional designs, is avoided. Simulations show that the proposed gate driver has a much improved driving speed in comparison...
This paper presents a new poly-Si thin film transistor (TFT) pixel circuit for active-matrix organic light-emitting diode (AMOLED) displays. The pixel circuit has a simple four-transistor configuration and is controlled by two adjacent gate scan pulses, allowing a small circuit area and simple driving scheme. Simulation results show that this pixel circuit can provide the OLED with a current non-uniformity...
Capacitance-voltage (C-V) and frequency dependent conductance-voltage (G-V) measurements have been carried out to investigate the charging and discharging effect induced by interface states and nanocrystalline Si (nc-Si) in floating gate MOS structures. Distinct conductance peaks are observed in the G-V curves for the floating gate with and without nc-Si dots. Based on the calculation of interface...
A new type of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with self-aligned metal electrodes (SAME) is systematically characterized. New device features different from conventional poly-Si TFTs are found, and are attributed to the presence of Schottky barriers at the channel ends.
Electron and hole mobility in sub-10nm silicon nanowire FETs on (100) SOI has been systematically investigated experimentally. The nanowire height of fabricated nanowire FETs is as low as 4 - 10nm and the minimum nanowire width is shrunk to 5nm. Higher hole mobility than (100) universal mobility is experimentally observed for the first time in 9nm-wide nanowire and even in 5nm-wide nanowire, while...
PIN tunneling field effect transistor (TFET) is one of the most promising devices due to its low sub-threshold swing. In this paper, using TCAD simulation, we investigate the doping and structure dependence of the electric field in PIN TFET. We show that an insertion of a thin N layer into PIN structure (i.e., PNIN TFET) not only enhances the drive current but also improves the reliability of the...
GaN is very promising for power switching transistors taking advantages of the high breakdown strength with high saturation electron velocity. The lateral and compact device configuration enables high speed switching with reduced on-state resistance and parasitic capacitance. In this paper, state-of-the-art device technologies of GaN transistor and its monolithic integration for switching applications...
In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic properties, source/drain series resistance (RSD), and driving current. The SDE-RDF induced variations of threshold voltage (Vth) and DIBL in SNWTs with different diameters are found to...
A new method for extraction of series resistance is proposed for poly-Si thin-film transistors. In this method, the extraction procedure is insensitive to the variation in effective channel length and device mobility, since both quantities are included in a single extracted parameter. The method has been successfully applied to a group of poly-Si TFTs with mask channel length from 2 to 30μm. Compared...
A simple top down method to fabricate an array of vertically stacked nanowires is presented. By taking advantage of the non-uniformity of the Inductive Coupled Plasma (ICP) etching process to form a scalloped sidewall followed by a subsequent stress limited oxidation step, a narrow silicon fin can be vertically patterned to form stacked nanowires with different cross-sectional shapes. The stacked...
Fabrication and performance of high-frequency 0.3-μm gate-length depletion-mode metamorphic Al0.50In0.50As/Ga0.47In0.53As high electron mobility transistors (mHEMT) grown by Metalorganic Chemical Vapor Deposition (MOCVD) on n-type silicon substrates is reported. Using a combined optical and e-beam photolithography technology, submicron mHEMT devices on Si have been achieved. A maximum trans-conductance...
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