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We theoretically investigate the mechanism of the electron rebound from the drain into the channel and its impact on the drain current in the nano-scale InGaAs MOSFETs by using the quantum corrected Monte Carlo (MC) simulation. The electrons almost ballistically transport in the channel at the gate length, Lg, of 10 nm. However the electron rebound becomes pronounced instead when the electrons degenerate...
We would like to report our approaches to realize epitaxially grown source toward high drain current in III-V MISFET. One approach is an InP/InGaAs composite channel MISFET with regrown InGaAs source/drain. When gate length of 150 nm was fabricated, Id at Vd = 0.8 V was 0.8 A/mm and maximum gm was 0.38 S/mm at Vd = 0.5 V. The other approach is vertical FET. In case of vertical FET with dual gate,...
Ultra-high-vacuum (UHV) deposited Ga2O3(Gd2O3) [GGO] has been employed for passivating InGaAs and Ge, without using any interfacial paissivation layers (IPLs). The GGO/InGaAs and /Ge metal-oxide-semiconductor capacitors (MOSCAPs) have exhibited low capacitance-equivalent-thickness (CET) of less than 1nm in GGO, low interfacial densities of states (Dit's) ~ 1011eV-1cm-2, and thermal stability at high...
CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of key devices for high performance and low power advanced LSIs in the future. In addition, the heterogeneous integration of these materials on the Si platform can provide a variety of applications from high speed logic CMOS to versatile SoC chips, where various functional devices can be co-integrated. In this presentation,...
High-performance implant-free In0.53Ga0.47As-channel MOSFETs grown on GaAs substrates by Metalorganic Chemical Vapor Deposition (MOCVD) are demonstrated. Atomic-layer-deposited (ALD) Al2O3 was used as gate dielectric on top of a δ-doped In0.53Ga0.47As/In0.51Al0.49As metamorphic heterojunction structures grown on GaAs substrates. A 1-μm gate-length MOSFET with 15nm Al2O3 shows a maximum drain current...
The principal obstacle to III-V compound semiconductors rivaling or exceeding the properties of Si electronics has been the lack of high-quality, thermodynamically stable insulators on III-V materials. For more than four decades, the research community has searched for suitable III-V compound semiconductor gate dielectrics or passivation layers. The research on ALD approach is of particular interest,...
In this paper, we discuss the research and development of several key process modules for realizing high-mobility III-V n-MOSFETs. Interface passivation technologies were developed to realize high quality gate stacks on III-V. InGaAs MOSFETs with in situ doped lattice-mismatched source/drain (S/D) stressors were demonstrated for reduction of S/D series resistance as well as channel strain engineering...
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