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The following topics are dealt with: planar SOI devices; SOI memories; SOI photonics, MEMS, sensors and circuits; materials and 3D technologies; multi-gate SOI devices; SOI radiation effects and RF applications; device characterization, reliability, and modeling.
The ability to fully leverage future CMOS technologies will require a proactive approach to aggressively manage power while characterizing and mitigating the various sources of technology uncertainty. Adaptive techniques that span the full design stack across technology, circuits, and systems/software are required for building future reliable systems. Moreover, the emerging trend of low-power, multi-core-based...
Beginning in the mid-1990s, Sandia National Laboratories began its migration to Silicon-on-Insulator (SOI) wafers to develop a radiation-hardened semiconductor process for sub-0.5mum geometries. Successfully radiation hardening SOI technologies enabled an in-house processing familiarity that exceeded our expectations by opening opportunities to improve other technologies. Rather than rely on a single...
Silicon-on-sapphire CMOS has always been an intriguing technology with prospects for applications in niche markets. In this paper, we summarize our work with SOS CMOS technology over the last two decades and identify opportunities where the unique physical properties of the sapphire substrate offer advantages in systems integration and packaging. We focus our discussion on two largely unexplored major...
We discuss key challenges for SOI CMOS to achieve sub-100 pA/m leakage current required for low-standby power applications. Recent 45 nm data is used to illustrate the importance of junction engineering to mitigate SOI floating body effect for low leakage design. With device scaling towards 22 nm node, both bulk and SOI technologies are expected to hit a fundamental GIDL limit. Extremely-thin body...
Dual stress liner process for high performance SOI CMOS technology at 32 nm technology node is improved through the use of dep-etch-dep, etch back, and spacer removal techniques. The stress benefit of DSL is preserved with improved gap fill for the manufacturing of sub-32 nm gate length transistors.
Integration of low-dielectric constant SiCOH dielectrics (k~3) adjacent to gate stacks is demonstrated using 65 nm technology. Substantial reductions in parasitic capacitances are achieved through reductions in the outer fringe component of the overlap capacitance and the capacitance between the gate stack and metal contacts. These results are consistent with modeling. Although this is demonstrated...
We demonstrate a simple and novel scheme to achieve high drain breakdown voltage (BV) in a high-speed silicon-on-insulator (SOI) logic technology. In an SOI device with two FETs in series, the common floating node provides a negative feedback that limits the increase of avalanche current. This unique property of SOI provides a way to enhance the breakdown voltage by simply adding more devices in series...
To address key challenges in transistor scaling [1,2], we have used 3D oxide bonding technology in a new way, to fabricate CMOS devices and circuits in which the gate is on the opposite side of the channel from the contacts between the FET and the first wiring level (Ml).
Detailed measurements of front and back channel characteristics in advanced SOI MOSFETs (ultrathin film, metal gate, selective epitaxy of source/drain) are used to reveal the transport properties at the corresponding Si/high-K (HfO2/HfSiON) and Si/SiO2 interfaces. Low-temperature operation magnifies the difference between these two interfaces in terms of carrier mobility, threshold voltage and subthreshold...
A scaled planar FBC technology with undoped-body is demonstrated featuring 10-nm BOX, 25-nm SOI, high-k and metal gate. Good agreement on retention window characteristics between measured data and simulations is achieved at multiple temperatures and illustrates Shockley-Read-Hall (SRH) recombination and generation dominated loss mechanism during hold condition. Optimization of Source-Drain (SD) and...
Cell array architecture for floating body RAM of 35 nm bit line half pitch is described. The quasi-non-destructive-read-out feature of floating body cell contributes to eliminating inter-bit line coupling noise in open bit line architecture without degrading the cycle time of the RAM.
A scaling scenario of fully-depleted floating body cell (FBC) is demonstrated in view of signal margin for stable array functionality. Measurement and numerical simulation reveal that the Vth variation of cell array transistors is mainly attributed to the random dopant fluctuation in channel region. By setting the channel impurity concentration in the order of 1016cm-3 or lower, Gbit array functionality...
In this work, we have compared different FB-RAM architectures. Whereas highly doped PDSOI devices show high programming window and retention times for long channel devices, the SOI FinFET devices with WFIN=25 nm can be scaled down to LG=50 nm while still maintaining high cell margins and retention times. For the latter devices optimization of the write and especially read bias conditions is needed.
The proposed selective-back gate bias technique using dual BOX improves SRAM stability, reduce leakage power, and enhances sub-array access speed while preserving overall area efficiency. TCAD simulations show that nominal Read SNM is improved by 37%, and the cell is very immune to process variations such as RDF, TSi, and TBOX. Thus, it is very suitable for high-performance on-chip cache and SOC embedded...
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