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A scaled planar FBC technology with undoped-body is demonstrated featuring 10-nm BOX, 25-nm SOI, high-k and metal gate. Good agreement on retention window characteristics between measured data and simulations is achieved at multiple temperatures and illustrates Shockley-Read-Hall (SRH) recombination and generation dominated loss mechanism during hold condition. Optimization of Source-Drain (SD) and...
In this work, we have compared different FB-RAM architectures. Whereas highly doped PDSOI devices show high programming window and retention times for long channel devices, the SOI FinFET devices with WFIN=25 nm can be scaled down to LG=50 nm while still maintaining high cell margins and retention times. For the latter devices optimization of the write and especially read bias conditions is needed.
Several methods have been investigated for gettering impurities during CMOS processing, in order to achieve high-quality oxides on thick SOI. The use of buried implants, buried polysilicon, surface implants, and isolation trenches was found to significantly improve the oxide quality in each case.
Body-to-Body leakage (BBL) in stacked transistor configuration has been characterized by different back gate biases (Vbg), SOI thicknesses, and poly spacings. BBL increases significantly from 65 nm to 45 nm node mainly due to smaller poly spacing and shallower S/D junctions. By implant optimization and reduction of the SOI thickness, BBL can be reduced below reverse junction leakage level.
We report the potential-based SOI-MOSFET model HiSIM-SOI, which solves the three surface potentials of the SOI-device accurately without sacrificing simulation time. The model implements the bias dependent dynamic depletion behavior, shifting between partially-depleted (PD) and fully-depleted (FD) conditions smoothly. It is also demonstrated that the floating-body effect can be accurately captured...
According to the CMOS device on SOI substrate (SOI CMOS device), we investigate the influence of holes accumulated in buried oxide film (BOX) under the radiation environment by monitoring leakage current with back bias. We confirmed that the leakage current has the colleration to total ionizing dose (TID). SOI CMOS assumed to be not good on TID, compared to bulk. But, we confirmed the tolerance to...
The extraction of the trap density on Ge/gate-stack (top) and Ge/BOX (bottom) interfaces of germanium-on-insulator pMOSFETs is shown using the Lim & Fossum model historically developed for fully depleted SOI devices. The doping and the thickness of the Ge film do not change significantly the top interface trap density. The bottom one is slightly raised by doping the Ge film. This method can be...
The parasitic resistance of the FinFET is investigated by the measurement based analysis. The RS/D model suggests that careful optimization as to the NiSi incorporation is necessary for the effective Rp reduction. The Rext seriously increases the Rp for TfinLt25 nm and also causes the Rp variability due to the Tfin variation.
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