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In this work, we have compared different FB-RAM architectures. Whereas highly doped PDSOI devices show high programming window and retention times for long channel devices, the SOI FinFET devices with WFIN=25 nm can be scaled down to LG=50 nm while still maintaining high cell margins and retention times. For the latter devices optimization of the write and especially read bias conditions is needed.
In this work, the influence of the temperature variation, in the range of 200K up to 380K, on the performance of biaxially strained FinFETs with high-kappa dielectrics (HfO2), TiN metal gate and undoped body is investigated. It is demonstrated that narrow FinFETs present slightly smaller improvement at lower temperatures on the maximum transconductance (and hence mobility) and transconductance-to-drain...
In this paper we present the first complex mixed-signal FinFET circuit (>1500 devices). Design and implementation aspects as well as measurement results of a 10-bit current- steering D/A converter are shown. The achieved performance proves the ability of recent FinEET technology to realize competitive mixed-signal circuits with large device count and wide range of device dimensions. Moreover the...
In this work, the possibility of achieving low Vt nMOS FinFET transistors through the use of a La2O3 dielectric cap, and the ability of co-integrating La2O3 capping with medium and low Vt pFinFET devices are investigated. A significant improvement in device performance was shown for thin La2O3 capping with CVD TaN electrode.
A detailed analysis about the impact of parasitic capacitances/resistances and fin geometry in FinFETs for RF applications has been presented. RF FinFETs should be designed with Tfin/Lg of 0.6 and AR of 3, along with minimal fin spacing of 50 nm to achieve higher fT and fMAX values. Although FinFET will always exhibit higher parasitics than an equivalent planar technology, reduction of RSD to ITRS...
An approach to nanoscale DG FinFET design for LP and HP nanoscale-CMOS applications via S/D engineering [i.e., control of NSD(y)] was proposed, and demonstrated to be viable by device simulations and measurements. The approach exploits the idea of allowing S/D dopants properly distributed in the channel for HP-Vt design. We demonstrated the design approach at the 45nm node. Scaling Lg to Lt10nm, as...
The parasitic resistance of the FinFET is investigated by the measurement based analysis. The RS/D model suggests that careful optimization as to the NiSi incorporation is necessary for the effective Rp reduction. The Rext seriously increases the Rp for TfinLt25 nm and also causes the Rp variability due to the Tfin variation.
The logic gate threshold voltage controllable single metal gate FinFET CMOS inverter constructed by the 3T-PMOS and 4T-NMOS have successfully been fabricated. The accurate current matching and the logic gate threshold voltage tuning by Vg2 in the 4T-NMOS have been demonstrated. A higher WF metal would be more suitable for the proposed FinFET CMOS.
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