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A scaled planar FBC technology with undoped-body is demonstrated featuring 10-nm BOX, 25-nm SOI, high-k and metal gate. Good agreement on retention window characteristics between measured data and simulations is achieved at multiple temperatures and illustrates Shockley-Read-Hall (SRH) recombination and generation dominated loss mechanism during hold condition. Optimization of Source-Drain (SD) and...
A comprehensive model is presented to analyze the 3D source-drain resistance of undoped double gated FinFETs. The model incorporates the contribution of the spreading resistance, sheet resistance and the contact resistance. The spreading resistance is modeled using a standard 2D model generalized to 3D. The contact resistance is modeled by generalizing the 1D tranmission line model to 2D and 3D with...
This paper talks about the developments in silicon photonic devices which exploit the inherent high refractive index contrasts achievable on an SOI platform. We will focus on the optical modulator which has been designed for speeds up to 40Gbps. We will also describe the design and performance of a photonic integrated transmitter chip, which has been demonstrated to transmit at an aggregate data rate...
In this work, fabrication of TSNWFET on SOI with down to 25-nm TiN surrounding gate and 8-nm silicon nanowires is reported with high manufacturability and improved device reliability including reduced junction and gate leakage currents by fully eliminating the bottom parasitic channel existing in previous TSNWFET on bulk Si. And high performance is also obtained to be 1124muA/mum and 1468muA/mum at...
The continued path on Moore's Law has increased the concern about soft errors, even in terrestrial applications. Multiple device (multiple bit) interactions and upsets are now one of the major challenges of analysis and mitigation in bulk CMOS devices. This is perhaps the major advantage for SOI with respect to single event effects. New SOI devices, including the MugFETS and ZRAMs, present opportunities...
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