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In summary, an improved process named SIMOX layer transfer is proposed. SOI wafer with the device layer thickness of 147.5plusmn3.1 nm has been fabricated with SLT process. SE result indicates that the device layer has excellent thickness uniformity. The results of TEM show sharp interfaces and defect-free device layer, revealing the perfect structure of SLT SOI.
This paper talks about the developments in silicon photonic devices which exploit the inherent high refractive index contrasts achievable on an SOI platform. We will focus on the optical modulator which has been designed for speeds up to 40Gbps. We will also describe the design and performance of a photonic integrated transmitter chip, which has been demonstrated to transmit at an aggregate data rate...
In this paper, the modeling, fabrication and optimization of the proposed nanobiosensor for detection of biomolecules such as DNA hybridization has been studied and different advantages and disadvantages of such a device are discussed. This paper outlines how the modulation of impedance in a novel silicon nanobridge (nanowire) biosensor can be used in characterizing biochemical species such as a antibodies/antigens...
In this paper, the design and fabrication of Silicon-On-Insulator scanning micromirrors that have high angular precision over a large scan angle is described. These microscanners are actuated by electrostatic comb drives, which consume minimum amounts of power. When driven by AC signals, these scanners have fast scan rates and large scan angles.
In this paper, the partially depleted SOI phototransistor has been used as a light intensity sensor. A pixel implementing the technique elaborated by L. Harik et al was designed and implemented on SOI technology. The circuit implements a first order Delta-sigma modulator. Measured data show flux densities as low as 3mW/m2 and an SNR of 60 dB.
We propose a novel substrate-bias control scheme for FD-SOI SRAM that suppresses inter-die variability and achieves low-voltage operation. Substrate-bias control circuits automatically detect an inter-die threshold-voltage variation, and then maximize read/write margins of memory cells. We confirmed that a 486-kb SRAM operates at 0.42 V, in which an FS/SF corners can be compensated as much as 0.14...
In this paper we present the first complex mixed-signal FinFET circuit (>1500 devices). Design and implementation aspects as well as measurement results of a 10-bit current- steering D/A converter are shown. The achieved performance proves the ability of recent FinEET technology to realize competitive mixed-signal circuits with large device count and wide range of device dimensions. Moreover the...
This paper presents the impact of varying both the architecture and the technology on the performance of the full adder. A 10% reduction in total power and 15.2% reduction in delay are gained by changing the architecture. While an average power reduction of 15.5% and 14.1% reduction in average delay are gained by using SOI layout and junction capacitances instead of bulk.
In the continuing thrust to extend Moorepsilas law, silicon is beginning to confront several issues that require innovative materials solutions to increase transistor and interconnect speeds while dealing with the increasing thermal loads of advanced microprocessors. The unsurpassed thermal, electrical and mechanical properties of diamond can be used to solve some of the thermal issues and enhance...
The successful fabrication of hybrid SOI-GeOI wafers is reported. Process alternatives are documented by detailed characterizations. This co-integration achieves high hole mobility in Ge islands and high electron mobility in Si islands.
A new Si-on-AlN substrate has been fabricated and characterised both electrically and thermally. Thermal properties of the new substrate have been identified with a thermal resistance reduced by half to 47.5 K/W compared to reference SOI. Further improvements in fabrication of these new SOI substrates with regard to the alpha-Si layer, oxide layer and in AlN film quality itself would utillise the...
Silicon-on-insulator (SOI) technologies have recently attracted interest in the development of next-generation high-performance micro-systems. The absence of latch-up, the reduced parasitic capacitance, the circuit isolation and multi-threshold devices are just a few of the advantages of this technology. This article introduces a flavor of SOI called silicon-on-sapphire (SOS), describing the fabrication...
This paper describe the process and test results after single tier circuit fabrication as well as after three-tier integration, determine impact of 3D vias on ring oscillator performance, and demonstrate functionality of single and multi-tier circuits of varying complexity.
Three topologies to globally distribute a clock signal in 3-D circuits have been evaluated. A 3-D test circuit, based on the MITLL 3-D IC manufacturing process, has been designed, fabricated, and measured and is shown to operate at 1.4 GHz. Clock skew measurements indicate that a topology that combines the symmetry of an H-tree on the second plane and local meshes on the other two planes will result...
The challenges of device scaling and short channel effects have necessitated the close examination of 3 dimensional processing. While this certainly comes with challenges in processing and metrology, it also comes with opportunities for new device paradigms and analysis methods. We will look at an historical perspective of 3D processing and further examine how to accurately ldquothinkrdquo 3D to achieve...
In this work, fabrication of TSNWFET on SOI with down to 25-nm TiN surrounding gate and 8-nm silicon nanowires is reported with high manufacturability and improved device reliability including reduced junction and gate leakage currents by fully eliminating the bottom parasitic channel existing in previous TSNWFET on bulk Si. And high performance is also obtained to be 1124muA/mum and 1468muA/mum at...
In this paper, we investigate the potentialities and properties of HfSiO/MG/cap/TiN gate stack devices, first by identifying the impact of the TiN thickness and its deposition procedure on the device characteristics, and by exploring the use of TaN vs. TiN as the 1st metal layer (MG). Deeper insight into the caps (e.g., Dy) diffusion mechanism is gained by: a) demonstrating stronger diffusion dependence...
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