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Beginning in the mid-1990s, Sandia National Laboratories began its migration to Silicon-on-Insulator (SOI) wafers to develop a radiation-hardened semiconductor process for sub-0.5mum geometries. Successfully radiation hardening SOI technologies enabled an in-house processing familiarity that exceeded our expectations by opening opportunities to improve other technologies. Rather than rely on a single...
Detailed measurements of front and back channel characteristics in advanced SOI MOSFETs (ultrathin film, metal gate, selective epitaxy of source/drain) are used to reveal the transport properties at the corresponding Si/high-K (HfO2/HfSiON) and Si/SiO2 interfaces. Low-temperature operation magnifies the difference between these two interfaces in terms of carrier mobility, threshold voltage and subthreshold...
In this paper, we present numerically calculated values of thermal resistances of Si BJT (or SiGe HBT) devices fabricated on bonded SOI substrates. Different lateral isolation schemes are studied, as well as different materials for the plane buried isolator that ensures dielectric vertical isolation of the Si device to the Si substrate. More specifically, we investigated sandwich stacks to replace...
In this paper, the design and fabrication of Silicon-On-Insulator scanning micromirrors that have high angular precision over a large scan angle is described. These microscanners are actuated by electrostatic comb drives, which consume minimum amounts of power. When driven by AC signals, these scanners have fast scan rates and large scan angles.
This paper presents high-Q and high current on-chip inductors integrated in a six copper metal level radio frequency (RF) back end of line (BEOL), including two 3 mum thick top metallizations, in an advanced high resistivity (HR) SOI CMOS technology. Inductors achieved on HR SOI CMOS technology using this optimized RF BEOL are reported, compared with standard BEOL, and firstly benchmarked with current...
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