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We have characterized the metal-NC high-k-dielectric flash memories on low-temperature UTB-TFTs. Combined with the advantage of low-voltage operations, the reported planar process is expected to be applicable for 3D integration to meet high-density flash memory requirements. Carrier transport was also confirmed to be Frenkle-Poole emission in (Ti,Dy)O and direct tunneling in Al2O3 due to the different...
Super fast Monte-Carlo techniques are applied to allow deeper insight to the yield of SOI domino circuit design techniques for SRAMs. For the first time, Read-before-Write in dual supply domino bit-select design is analyzed in the presence of floating body effects, hysteretic and process variations. The methodology provides greater ability to alleviate non-functionality by identifying yield-optimized...
Several methods have been investigated for gettering impurities during CMOS processing, in order to achieve high-quality oxides on thick SOI. The use of buried implants, buried polysilicon, surface implants, and isolation trenches was found to significantly improve the oxide quality in each case.
Body-to-Body leakage (BBL) in stacked transistor configuration has been characterized by different back gate biases (Vbg), SOI thicknesses, and poly spacings. BBL increases significantly from 65 nm to 45 nm node mainly due to smaller poly spacing and shallower S/D junctions. By implant optimization and reduction of the SOI thickness, BBL can be reduced below reverse junction leakage level.
A comprehensive model is presented to analyze the 3D source-drain resistance of undoped double gated FinFETs. The model incorporates the contribution of the spreading resistance, sheet resistance and the contact resistance. The spreading resistance is modeled using a standard 2D model generalized to 3D. The contact resistance is modeled by generalizing the 1D tranmission line model to 2D and 3D with...
Both structural and bias asymmetries in double-gate (DG) SOI MOSFET have been critically examined for the sub-60 mV/dec subthreshold swing (SS) possibility. Physical mechanisms are illustrated to explain the inability of all the analyzed structural asymmetries and the feasibility with the bias asymmetries.
In this work, the influence of the temperature variation, in the range of 200K up to 380K, on the performance of biaxially strained FinFETs with high-kappa dielectrics (HfO2), TiN metal gate and undoped body is investigated. It is demonstrated that narrow FinFETs present slightly smaller improvement at lower temperatures on the maximum transconductance (and hence mobility) and transconductance-to-drain...
The improved immunity of FD SOI technology against short-channel effects has been shown to offer a great interest for subthreshold logic in terms of delay and energy per operation at medium throughputs (108 Op/s). Moreover, the combination of an undoped channel with a metal gate extends this benefit to lower throughputs by a reduction of the minimum functional Vdd and static energy. This makes FD...
We report the potential-based SOI-MOSFET model HiSIM-SOI, which solves the three surface potentials of the SOI-device accurately without sacrificing simulation time. The model implements the bias dependent dynamic depletion behavior, shifting between partially-depleted (PD) and fully-depleted (FD) conditions smoothly. It is also demonstrated that the floating-body effect can be accurately captured...
The degradation of SRAM stability with gate length and supply voltage scaling is a serious concern [1-7]. In this work, we analyze the impact of gate-underlap design [8-9] on the performance of 6-T SRAM cell, based on independently addressable 22 nm Double Gate (DG) SOI MOSFETs for low voltage operation. The trade-offs associated with read/write requirements have been evaluated in terms of eight performance...
This paper describes two novel sub-32 nm current (CSA) and voltage (VSA) sense amplifiers in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. The proposed sense amplifiers (SA) need 40% to 4 times less power, achieve a 10-15% increase in speed and have a 2.5 to 3.5 times larger tolerance to Vth and L mismatch compared to published...
The pseudo-MOS transistor (Psi-MOSFET) is a quick technique for monitoring SOI wafers. Based on Poisson numerical simulations, we derive updated models for the characterization of ultrathin films, accounting for the density of traps of passivated and nonpassivated surfaces. These analytical models match the experimental results and are useful for accurate parameter extraction.
In this paper, we present numerically calculated values of thermal resistances of Si BJT (or SiGe HBT) devices fabricated on bonded SOI substrates. Different lateral isolation schemes are studied, as well as different materials for the plane buried isolator that ensures dielectric vertical isolation of the Si device to the Si substrate. More specifically, we investigated sandwich stacks to replace...
Thermal characterization of the new Si-on-SiC hybrid substrate has shown thermal properties superior in comparison with SOI. The thermal resistivity was shown to be a factor of four lower, and the lateral thermal spread was much more efficient, as is explained by the excellent heat conductivity of the SiC substrate. These results correspond well to the absence of MOSFET self-heating effects for the...
In this work, we investigate the channel backscattering characteristics for SOI MOSFETs using a new temperature-dependent method with consideration of self-heating effects. The temperature sensitivity of mobility (beta, mu0propTbeta) is self-consistently determined along with the backscattering coefficient rsat.
The leakage current of SOI based Floating Body Memory (FBM) has been modeled. The model takes into account oxide/SOI interface traps (Dit) and Electric Field Enhanced (EFE) generation of electron hole pairs (EHPs) from trap states via the Poole-Frenkel Effect (PFE). This model has been used to improve the retention time of Z-RAM by a reduction of both Dit and electric field. It can also be extended...
SOI technology is now emerging as a promising one for the integration of RF front-end modules, mainly for antenna switches and power amplifiers (PAs). This paper reviews the performances of STMicroelectronics 0.13 mum High Resistivity (HR) SOI CMOS technology and discusses the potentiallity for SOI technology to capture RF front-end business in the near future.
We present a novel method to realize 3D adiabatically Spot-Size Converter (SSC) structures by standard silicon micromachining technics, for efficient coupling from single-mode fiber or free-space to silicon photonic chip. The SSC is comprised of I/O waveguides and a 3D tapered coupler on silicon-on-insulator (SOI) substrate. The dimensions are decreased linearly in both vertical and horizontal directions...
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