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Beginning in the mid-1990s, Sandia National Laboratories began its migration to Silicon-on-Insulator (SOI) wafers to develop a radiation-hardened semiconductor process for sub-0.5mum geometries. Successfully radiation hardening SOI technologies enabled an in-house processing familiarity that exceeded our expectations by opening opportunities to improve other technologies. Rather than rely on a single...
We present a novel method to realize 3D adiabatically Spot-Size Converter (SSC) structures by standard silicon micromachining technics, for efficient coupling from single-mode fiber or free-space to silicon photonic chip. The SSC is comprised of I/O waveguides and a 3D tapered coupler on silicon-on-insulator (SOI) substrate. The dimensions are decreased linearly in both vertical and horizontal directions...
In this paper, the partially depleted SOI phototransistor has been used as a light intensity sensor. A pixel implementing the technique elaborated by L. Harik et al was designed and implemented on SOI technology. The circuit implements a first order Delta-sigma modulator. Measured data show flux densities as low as 3mW/m2 and an SNR of 60 dB.
In the continuing thrust to extend Moorepsilas law, silicon is beginning to confront several issues that require innovative materials solutions to increase transistor and interconnect speeds while dealing with the increasing thermal loads of advanced microprocessors. The unsurpassed thermal, electrical and mechanical properties of diamond can be used to solve some of the thermal issues and enhance...
A new Si-on-AlN substrate has been fabricated and characterised both electrically and thermally. Thermal properties of the new substrate have been identified with a thermal resistance reduced by half to 47.5 K/W compared to reference SOI. Further improvements in fabrication of these new SOI substrates with regard to the alpha-Si layer, oxide layer and in AlN film quality itself would utillise the...
Silicon-on-insulator (SOI) technologies have recently attracted interest in the development of next-generation high-performance micro-systems. The absence of latch-up, the reduced parasitic capacitance, the circuit isolation and multi-threshold devices are just a few of the advantages of this technology. This article introduces a flavor of SOI called silicon-on-sapphire (SOS), describing the fabrication...
In this work, fabrication of TSNWFET on SOI with down to 25-nm TiN surrounding gate and 8-nm silicon nanowires is reported with high manufacturability and improved device reliability including reduced junction and gate leakage currents by fully eliminating the bottom parasitic channel existing in previous TSNWFET on bulk Si. And high performance is also obtained to be 1124muA/mum and 1468muA/mum at...
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