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The ability to fully leverage future CMOS technologies will require a proactive approach to aggressively manage power while characterizing and mitigating the various sources of technology uncertainty. Adaptive techniques that span the full design stack across technology, circuits, and systems/software are required for building future reliable systems. Moreover, the emerging trend of low-power, multi-core-based...
Silicon-on-sapphire CMOS has always been an intriguing technology with prospects for applications in niche markets. In this paper, we summarize our work with SOS CMOS technology over the last two decades and identify opportunities where the unique physical properties of the sapphire substrate offer advantages in systems integration and packaging. We focus our discussion on two largely unexplored major...
Dual stress liner process for high performance SOI CMOS technology at 32 nm technology node is improved through the use of dep-etch-dep, etch back, and spacer removal techniques. The stress benefit of DSL is preserved with improved gap fill for the manufacturing of sub-32 nm gate length transistors.
SOI technology is now emerging as a promising one for the integration of RF front-end modules, mainly for antenna switches and power amplifiers (PAs). This paper reviews the performances of STMicroelectronics 0.13 mum High Resistivity (HR) SOI CMOS technology and discusses the potentiallity for SOI technology to capture RF front-end business in the near future.
This paper presents high-Q and high current on-chip inductors integrated in a six copper metal level radio frequency (RF) back end of line (BEOL), including two 3 mum thick top metallizations, in an advanced high resistivity (HR) SOI CMOS technology. Inductors achieved on HR SOI CMOS technology using this optimized RF BEOL are reported, compared with standard BEOL, and firstly benchmarked with current...
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