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The ability to fully leverage future CMOS technologies will require a proactive approach to aggressively manage power while characterizing and mitigating the various sources of technology uncertainty. Adaptive techniques that span the full design stack across technology, circuits, and systems/software are required for building future reliable systems. Moreover, the emerging trend of low-power, multi-core-based...
The proposed selective-back gate bias technique using dual BOX improves SRAM stability, reduce leakage power, and enhances sub-array access speed while preserving overall area efficiency. TCAD simulations show that nominal Read SNM is improved by 37%, and the cell is very immune to process variations such as RDF, TSi, and TBOX. Thus, it is very suitable for high-performance on-chip cache and SOC embedded...
We present an on-chip word line (WL) dual supply system for server class embedded DRAM (eDRAM) applications. The design consists of switched capacitor charge pumps, voltage regulators, reference and clock circuits. Charge pump engines feature efficient charge transfer and energy conversion, boosting unregulated rails to 1.8x supply. At vdd=1 V, regulated high (1.5 to 1.7 V) and low (-0.3 to -0.6 V)...
Independently-controlled double-gate devices using asymmetrical (n+/p+) gates are applied to the design of a novel VT-controlled voltage controlled oscillator (VCO). The VCO supports high operating frequencies and a wide tuning range. The back gates of the asymmetrical double-gate devices are used to modulate the threshold voltages of the front gate devices. A two-fold frequency tuning range is observed...
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