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The ability to fully leverage future CMOS technologies will require a proactive approach to aggressively manage power while characterizing and mitigating the various sources of technology uncertainty. Adaptive techniques that span the full design stack across technology, circuits, and systems/software are required for building future reliable systems. Moreover, the emerging trend of low-power, multi-core-based...
Cell array architecture for floating body RAM of 35 nm bit line half pitch is described. The quasi-non-destructive-read-out feature of floating body cell contributes to eliminating inter-bit line coupling noise in open bit line architecture without degrading the cycle time of the RAM.
In this work, we have compared different FB-RAM architectures. Whereas highly doped PDSOI devices show high programming window and retention times for long channel devices, the SOI FinFET devices with WFIN=25 nm can be scaled down to LG=50 nm while still maintaining high cell margins and retention times. For the latter devices optimization of the write and especially read bias conditions is needed.
The proposed selective-back gate bias technique using dual BOX improves SRAM stability, reduce leakage power, and enhances sub-array access speed while preserving overall area efficiency. TCAD simulations show that nominal Read SNM is improved by 37%, and the cell is very immune to process variations such as RDF, TSi, and TBOX. Thus, it is very suitable for high-performance on-chip cache and SOC embedded...
Super fast Monte-Carlo techniques are applied to allow deeper insight to the yield of SOI domino circuit design techniques for SRAMs. For the first time, Read-before-Write in dual supply domino bit-select design is analyzed in the presence of floating body effects, hysteretic and process variations. The methodology provides greater ability to alleviate non-functionality by identifying yield-optimized...
The degradation of SRAM stability with gate length and supply voltage scaling is a serious concern [1-7]. In this work, we analyze the impact of gate-underlap design [8-9] on the performance of 6-T SRAM cell, based on independently addressable 22 nm Double Gate (DG) SOI MOSFETs for low voltage operation. The trade-offs associated with read/write requirements have been evaluated in terms of eight performance...
We propose a novel substrate-bias control scheme for FD-SOI SRAM that suppresses inter-die variability and achieves low-voltage operation. Substrate-bias control circuits automatically detect an inter-die threshold-voltage variation, and then maximize read/write margins of memory cells. We confirmed that a 486-kb SRAM operates at 0.42 V, in which an FS/SF corners can be compensated as much as 0.14...
This paper describe the process and test results after single tier circuit fabrication as well as after three-tier integration, determine impact of 3D vias on ring oscillator performance, and demonstrate functionality of single and multi-tier circuits of varying complexity.
The continued path on Moore's Law has increased the concern about soft errors, even in terrestrial applications. Multiple device (multiple bit) interactions and upsets are now one of the major challenges of analysis and mitigation in bulk CMOS devices. This is perhaps the major advantage for SOI with respect to single event effects. New SOI devices, including the MugFETS and ZRAMs, present opportunities...
Partially depleted (PD) SOI CMOS technology has provided great flexibility to extend the performance of high density SRAM and leading edge microprocessors in various CMOS microelectronics products. In today's ASICs for defense electronics embedded 6T SOI SRAMs are used extensively and the SEU performance must be understood. The purpose of this paper is to present a rudimentary methodology for estimating...
Ultra-scaled Z-RAM cells based on MuGFETs are demonstrated for the first time. Effects of physical parameters such as channel doping concentration, fin width, and gate length on Z-RAM cell performance are discussed. Transient measurements and simulations prove that the basic operational principles are effective on Z-RAM cells with a gate length down to 12.5 nm.
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