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Performance limit of Tri-Gate (TG) and Double Gate (DG) SOI FinFETs have been compared in terms of ballistic current which is calculated using a modified model shown for conventional MOSFET. Such a simple model for calculating ballistic current in nanoscale multigate MOSFETs is yet to be reported. Comparison of the ballistic current for different Si fin thicknesses reveals that for decreasing fin...
A numerical model is developed for solving two dimensional Poisson-Schrodinger equation in depletion-all-around (DAA) operation of n-channel four gate transistor (G4FET) by finite element method using COMSOL with MATLAB. The results from this model can be used to calculate ballistic drain current by mode-space approach. Potential distribution, conduction band profile, eigen energy profile and wave...
Transmission coefficient of electrons in an asymmetrical double-barrier hetero-structure has been calculated for different barrier widths, well widths, barrier-material compositions and applied voltages. These calculations are done using transmission line analogy of resonance tunneling phenomena and the results are used to show the effects of these variable parameters on transmission coefficient in...
The gate C-V characteristics of MOS device with ultrathin gate dielectrics and different types of non-uniform substrate doping profile with quantum mechanics (QM) treatment is presented. Self-consistent solution of Schrodinger's and Poisson's equations with wave function penetration are used to determine the MOS electrostatics, and results show that at low-frequency the C-V characteristic curves depend...
Lateral channel engineering utilizing halo-pocket implant surrounding drain and source regions is effective in suppressing short channel effects. However, the reported model cannot be extended further to the pocket implantation, where inhomogeneity along the channel is the main cause for the reverse short channel effect (RSCE). A strong reverse short channel effect suppresses the short channel effect...
Performance limit of tri-gate (TG) and double gate (DG) SOI FinFETs have been compared in terms of ballistic current which is calculated by using a modified model shown for conventional MOSFET. Such a simple model for calculating ballistic current in nanoscale multigate MOSFETs is yet to be reported. Comparison of the ballistic current for different Si fin thicknesses reveals that for decreasing fin...
Capacitance-voltage (C-V) characteristics of triple-gate (TG) and double gate (DG) silicon-on-insulator (SOI) FinFETs having sub 10 nm dimensions are obtained by self consistent method using coupled Schro??dinger-Poisson solver taking into account quantum mechanical effects. Though self-consistent simulation to determine current and short channel effects in these devices has been reported in recent...
Carbon nanotube (CNT) is one of the front line candidates for a possible replacement. Remarkable electronic and mechanical properties of CNTs make them promising building blocks for future nanoelectronics. Failure to develop room-temperature multiwalled (MW) carbon nanotube field-effect transistors (CNTFETs) because of large radii corresponding to small band gap (~ few KT) encouraged researchers to...
The quantum definition based threshold voltage has been evaluated for triple-gate (TG) SOI FinFETs using self-consistent Schrodinger-Poisson solver. Although a new quantum definition of threshold voltage for multiple gate SOI MOSFETs has been provided in recent literature, in-depth analysis of quantization effects on threshold voltage calculation for highly scaled TG FinFETs is yet to be done. In...
A quantum mechanical (QM) self-consistent model is developed for nano-MOS devices for high-κ insulator including wave function penetration effect into the gate dielectrics. The effects of different types of interface trap distributions are incorporated. It has been observed that capacitance-voltage (C-V) characteristics are sensitive to the interface trap distribution. Simulated results has been compared...
The effects of uniaxial strain on the band structures of Lt100Gt silicon nanowires of width 2.75 - 3.84 nm are studied using sp3d5s* orbital basis atomistic tight binding approach. The conduction band edge at Gamma point has almost no variation with strain and the second valley located at 0.36timespi/a of the wire Brilluoin moves down in energy with both compressive and tensile strains. The top valence...
The Capacitance-Voltage (CV) characteristics of n-channel Double Gate (DG) MOS structures are investigated. An accurate and efficient fully coupled 1-D Schrodinger-Poisson self-consistent solver has been used. The numerical solver employs finite element method to calculate different electrostatics of n-channel DGMOS structures. The CV characteristics are modeled by taking the effect of interface trapped...
Gate capacitance versus voltage (C-V) characteristics for double gate MOSFETs with uniaxially strained silicon substrate are presented incorporating wave function penetration effect. Changes in capacitance with stress levels up to 5 GPa are studied. Physical insights of the capacitance value change are also discussed. Contributions of band splitting and effective mass change in C-V due to uniaxial...
The effects of gate length Lg, gate dielectric constant isinox, gate oxide thickness tox, and sourc/drain doping concentration on inverse subthreshold slope and on/off current ratio of a top gate silicon nanowire on insulator device are studied using three dimensional quantum simulation. The variation of inverse subthreshold slope and on/off current ratio are very sensitive to gate length, gate dielectric...
In depletion-all around (DAA) operation of SOI four-gate transistor (G4-FET), the conducting channel can be surrounded by depletion regions induced by independent vertical MOS gates and lateral JFET gates. This enables majority carriers to flow through the volume of the silicon film far from both silicon/oxide and p+ gate/n-channel interfaces. A numerical model using FEMLAB with MATLAB is developed...
A simple and efficient method to calculate the gate leakage current of an ultra-thin body double gate MOS structure on (111) crystallographic orientation, incorporating quantum mechanical effects, is presented. Using an accurate and numerically efficient fully coupled one dimensional Schrodinger-Poisson self-consistent solver, the gate leakage current have been calculated and presented for different...
A study of dependence of wave function penetration effects on the gate capacitance of nanoscale DG MOSFETs on body-thickness, silicon surface orientation and the choice of high-kappa gate oxide material is presented. Gate capacitance increases when wave function penetration is incorporated. Wave function penetration effects on gate capacitance at low gate biases becomes more dominant with the scaling...
Using the Schrodinger-Poisson solver and the transmission line analogy, we have demonstrated an efficient technique for predicting direct tunneling gate leakage current for double gate MOS structures. As FEMLAB was used for solving the two equations, this technique is much faster than the conventional tools. Specifically the model can be used for modeling the tunneling currents for the substrate inversion...
A Quantum Mechanical model is presented to describe the post Soft Breakdown (SBD) phenomena for MOS structure with ultrathin high-k gate dielectrics. We model the SBD event by considering a lowered barrier height at the SBD spot area. The current density through fresh stack gate oxide area and the SBD area are evaluated using a Quantum Mechanical Wave Impedance method. Simulated results for post SBD...
We present the effect of wavefunction penetration on C-V characteristic of ultra-thin body double gate MOSFET using an accurate and numerically extremely efficient fully coupled one dimensional Schrodinger-Poisson self-consistent solver. Penetration effects have been studied and presented for different values of dielectric and silicon body thickness.
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