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The following topics are dealt with: semiconductor transistors; mixed signal integrated circuit; semiconductor device metallization and interconnection; semiconductor doping; power amplifiers; microwave and RF devices; CMOS integrated circuits; and analog-digital and digital-analog conversion.
Summary form only given. Semiconductors have two types of charge carriers, electrons and holes. Therefore, the complete semiconductor transistors are always bipolar, that is, its electrical characteristics contain both electron and hole currents controlled by changing the spatial distributions of both electron and hole charges using externally applied electric field to the semiconductor. The two forms...
Analog design issues, impacts of scaling on power consumption in analog circuit and device performance in nanoscale CMOS technologies are discussed. An example of simple and effective digital calibration scheme will be explained as a method of overcoming power device performance in the technology. Low voltage RF circuits for GPS and mobile TV applications and analog circuits that avoid operational...
This work reports a new model parameter extraction scheme for multi-finger MOS transistors operated in the radio-frequency (RF) range. The drain parasitic inductance, intrinsic capacitance, channel resistance, gate resistance, drain resistance, and source resistance are determined from the scattering parameters measured on RFMOS transistors with channel length of 90 nm, 100 nm and 110 nm with different...
This paper presents a new and more accurate potential based model for bulk MOSFET compared to the traditional charge-sheet surface potential model. The channel potential of the bulk MOSFET is obtained by solving Poisson equation and an accurate current expression is obtained base on it. Taking Pao-Sah model as a standard, the relative errors of the charge-sheet model may be as large as 4% in the saturation...
The performance of the manufacturing process in semiconductor determines the overall manufacturability of the process. It has been known that pattern missing and defects could be prevented by optimal the process module tuning. The abnormal pattern collapse observed in this process and numerous defects could be prevented by optimizing the fabrication process module tuning. To successfully integrated...
An analytical surface potential based current model for lateral gradual doping channel in LDMOS (lateral gradual doping MOSFETs) is developed. The position dependent parameters and build in electric field induced by the gradual doping profile are taken into account in derivation of a surface potential equation. Proper approximations are made in integration of the drift-diffusion current. The model...
With the reduction of interconnect dimensions, time-dependent dielectric breakdown (TDDB) has become more important. An improved TDDB lifetime model is proposed according to a physics mechanism based on the model of Wen Wu, et al.. The TDDB lifetime temperature dependence obtained by the original model is contrary to the experimental data. The improved model presented here introduces a correctional...
A low-voltage low-power high-efficiency squarer circuit used as energy collector for 3.1-5 GHz non-coherent UWB applications. The squarer circuit is based on flipped voltage follower circuit, whose bandwidth is extended higher than 5 GHz by choosing device length and bias current properly. The proposed squarer circuit is implemented in 65 nm CMOS process and the transistor level circuit simulation...
Silicon carbide (SiC) metal-semiconductor field effect transistors (MESFET) is a perfect choice for designing class-E power amplifiers (PA) due to its high breakdown voltage and low output capacitance. In this paper, a transmission-line class-E PA employing SiC MESFET is designed, and transistor parameters are discussed. The proposed PA has been tested with advanced design system (ADS), the peak power...
A novel approach to design millimeter-wave passive filters is presented using composite right/left-handed (CRLH) structures in a standard CMOS process. The filter is composed of left-handed open split-ring resonators (OSRR) or open complementary split-ring resonators (OCSRR). Such approach leads to a significant reduction in the on-chip area of the filter. It is also straightforward to construct similar...
New integration technologies yield devices capable to perform at very high frequencies. However shrinked dimensions also result in modest maximum operating voltages. Switched capacitor circuit techniques are associated with low frequency operation but when implemented in those advanced CMOS technologies are able to operate at GHz frequencies. Integrated RF active mixers are always based on circuit...
A CMOS RF receiver for digital radio broadcasting DRM and DAB applications is presented that contains an RF front-end, an analog baseband, a frequency synthesizer, and a controlling logic unit. In the RF front-end, the noise figure (NF) is minimized by a noise-canceling technology, and the IP3 is improved by using differential multiple gate transistors (DMGTR). The analog baseband consists of an image-rejection...
ULTRA-SOI is a new generation of the channel-potential-based non-charge-sheet model for the dynamic depletion (DD) Silicon-On-Insulator (SOI) MOSFET, developed by TSRC group in EECS department of Peking University with many year efforts. The model is formulated with a fully physical derivation from the Poisson's equation to solve the potential along the vertical direction of the silicon film. The...
As the technology node advances to the next generation, one of the biggest challenges is to achieve minimum pitch while maintaining device performance. This paper describes the details of a novel manufacturing process integration of complementary metal oxide semiconductor (CMOS) transistor architecture, which is incorporated into a sub-micron logic technology on 300 mm wafers. As the gate length is...
Numerical simulation study on electron mobility in independent DG MOSFETs with back gate biased in accumulation, flatband and inversion operation regions is presented in this paper. A numerical simulation program of the electron transport in the independent DG MOSFETs, which includes both phonon and surface roughness scattering mechanisms, is developed. From it, the dependence characteristics of the...
A generic DG MOSFET analytic model with vertical electric field induced mobility degradation effects is proposed and verified in this paper. It is shown that the proposed model is valid for different operation modes including symmetric DG (sDG), asymmetric DG (aDG) and independent DG (iDG). Extensive two-dimensional (2-D) device simulation is performed to verify the proposed model.
In this paper, a novel device structure called dual-material gate SOI MOSFET (DMG SOI MOSFET) is proposed to restrain drain-induced barrier lowering (DIBL) and short-channel effect (SCE) for the advanced nanometer process. The analytical threshold voltage model of novel structure device is presented, and the electrical characteristics are analyzed. The DMG SOI MOSFET with high k dielectric shows better...
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