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In this paper, the microwave performance of coplanar waveguides (CPWs) fabricated on high-resistivity silicon (HRS) substrates with various polysilicon film thicknesses was investigated. CPWs were fabricated on p-type silicon substrates with resistivities of 6000-8000 ??-cm. Polysilicon films with thicknesses ranging from 100 to 900 nm were deposited by LPCVD, in which a 300 nm-deposited polysilicon...
A new family of crystalline oxides is identified that provide a method of producing complementary memristance (both n and p-type having been demonstrated) with unusually large demonstrated memristance behavior. To the best of our knowledge, these are the only devices having a large enough memristance to have measureable memristance at the macroscopic (10's to 100's of um device size) scale. Additionally,...
In this work, the lateral InGaAs tunnel FET is configured and sized to enable gate control of the Zener (reverse bias) tunneling current. The p+InGaAs transistor channel is 4 nm thick with a n+p+ source injector and a thin 3/3 nm HfO2/Al2O3 high-k gate dielectric. Atomic-layer deposition (ALD) is used to deposit the gate dielectric.
The ability to accurately determine the breakdown voltage of microwave transistors is critical to the design of high power microwave amplifiers. The optimal bias point and output impedance should be selected to ensure that the load line of the device during peak output power does not intersect the portion of the IV curve where the device breaks down. This paper presents a technique to determine a...
In conclusion, PDMS-encapsulated CNT thin film shows excellent linear temperature sensitivity on the flexible substrate and each node shows good temperature sensing performance. Moreover, we successfully demonstrated a flexible temperature sensor array by using only solution process which will play a key role in low cost and simple future fabrication process development in flexible electronics.
Epitaxial graphene channel top-gate FETs on Si substrates are fabricated and their transistor operation is observed. Although the device characteristics is still primitive, this approach is a promising way to put graphene to the mainstream of the semiconductor manufacturing of the beyond-CMOS era.
The paper presents the feasibility of a 1200-V normally-OFF VJFET based on the manufacturable single-implant no-epitaxial-regrowth design. For efficient power switching (low gate current, low on-state resistance, low switching losses, and high current-gain), the VJFET gate must be biased below its built-in potential value (unipolar mode operation). In unipolar mode, 1200-V recessed-implanted-gate...
Single-walled carbon nanotubes (SWNTs) are rolled cylinders of monolayer graphene with high electron mobilities and a potentially large bandgap. Therefore, their operation speeds and current on/off ratios make them promising for next generation field-effect transistor devices. Making SWNTs a potential wafer-scale nanotechnology requires control of their chirality, density, placement, and alignment...
The authors have fabricated silicon nanowire (SiNW) based Al2O3/HfO2/SiO2 nonvolatile-memory (NVM) cells with varying HfO2 trapping layer thickness have been fabricated by using self-aligning approach. The cells exhibit excellent characteristics such as fast programming/erasing (P/E) speeds, good endurance and excellent retention. The P/E speed is not sensitive to the HfO2 layer thickness. The magnitude...
In here we present a way to calculate the electrostatic potential of Schottky barrier double-gate MOSFETs (SB-DG-MOSFET) in subthreshold region. Due to increasing source/drain (S/D) parasitic resistance, gate oxide leakage and degraded device performance caused by short channel effects (SCE) the technological limits for standard bulk will be reached soon. Therefore substantial changes regarding device...
In the present work, undoped CuxO thin films were deposited by pulsed laser deposition on glass and SiO2 substrates, at a constant oxygen partial pressure of 40Pa and at constant temperature of 200??C. The surface morphology of the deposited thin films was investigated by atomic force microscopy (AFM) in contact mode. The paper shows the 3D AFM images of CuxO thin films deposited on glass and SiO2...
The authors study the simplest but scientifically relevant case, where in the absence of capping layers or any other precautions, strain relaxation by film patterning and high temperature annealing can be observed. The thermal stability of bi-axial strain is maintained solely by a nonepitaxial bonded interface with the amorphous buried oxide in sSOI after patterning and subsequent high temperature...
The SiO2/SiC interface limits optimum SiC MOSFET performance due to a high density of interface states (D????), which is reduced in devices that receive post-oxidation NO-annealing. Also, the interface state density in the 6H polytype is generally lower, approaching that of the NO treated 4H. In this work, interface states are investigated in both as-oxidized (AO) and NO-annealed (NO) MOS capacitors...
Modifying the electrical properties of the silicon interface is of prime interest for next generation electronics. Scaling of conventional electronics is increasing the importance of electronic contributions from the near surface region while bulk contributions are becoming less important. We report a detailed ultraviolet photoelectron spectroscopy (UPS) and X-ray photoelectron spectroscopy (XPS)...
A novel electrically driven molecular rotor device has been designed and fabricated. NDR behaviors were observed owing to the rotation motion on the Cu axel. This is the first time that a rotation induced NDR effect on a solid support was observed. The rotation of the molecules was also confirmed using the optical absorption spectroscopy. From temperature dependence measurements, the activation energy...
Multiple-gate transistors are considered as very promising candidates for the 22 nm technological node. They are named Triple-gate FETs (TGFETs) when the gate controls three sides of the silicon body; if the channel etch process step penetrates in the Buried Oxide (BOX), the transistor is named Pi-gate FET. There is currently a strong need for compact models of such architectures, in order to evaluate...
The conduction channel of a field effect transistor (FET) can act as a plasma resonator for density oscillations in a quasi-two-dimensional electron gas. It has been proposed and demonstrated experimentally with the semiconductor transistor structures, that the hydrodynamic nonlinearities of the plasma transport can have a rectifying effect and induce a constant source-to-drain voltage in response...
Recently a new photodetector design based on quantum dots and resonant-tunneling diode (QDRTD) was proposed by Shields et al. which demonstrated high detection efficiency and a resolution to the single photon level. Different from the avalanche photo diode (APD) based photodetector, the detection mechanism of this device is to sense the change of the resonant tunneling current across the double barrier...
An AlGaN/GaN high electron mobility transistor (HEMT) model with temperature compensation is proposed. The simulation and experimental data are in close agreement within the measured temperature range. Despite of drain current degradation, the characteristics exhibit high temperature compatibility of AlGaN/GaN HEMTs.
To meet low power circuit requirements, increased channel mobility is required to boost transistor performance and reduce Vdd for lower power dissipation without performance penalty. SOI and more advanced engineered substrates developed on the SOI platform provide solutions for 32 technology nodes and beyond. The options include process-induced strain, biaxial strain virtual substrates, modification...
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