Capacitance-voltage (C-V) characteristics of triple-gate (TG) and double gate (DG) silicon-on-insulator (SOI) FinFETs having sub 10 nm dimensions are obtained by self consistent method using coupled Schro??dinger-Poisson solver taking into account quantum mechanical effects. Though self-consistent simulation to determine current and short channel effects in these devices has been reported in recent literature, C-V characterization, which is essential for parameter extraction, high frequency performance evaluation and device modeling, is yet to be done using self-consistent method. We investigate here the C-V characteristics of both these structures with the variation of an important process parameter, the silicon film or fin width.