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The III -nitrides AIN, GaN, InN and their alloys are a novel family of semiconductor materials for optoelectronics as well as for electronics. GaN-based high electron mobility transistors (HEMTs) have shown superior power density and operating temperatures at frequency ranges that are beyond the limits of devices fabricated from Si and other III-V materials. This paper presents the advances in the...
In this talk, three main topics including the CMOS implementation of neuromorphic chips, focal-plane motion sensors, and implantable retinal chips for visual prostheses are addressed. A CMOS design methodology for implementing CMOS neuromorphic chips which imitate the ON brisk transient ganglion cell (GC) set of rabbits' retinas is presented in the first part. Retina is the most important preprocessor...
The interaction of surface plasmon polariton (SPPs) on a periodic array of metal holes is investigated in theory and experiment. Extraordinary transmission through a silver film perforated with square and rectangular shaped hole arrays in a square lattice was demonstrated. When the squared hole size is close to a half lattice constant all, the split of the degenerate (plusmn1,0) Ag/Si and (0,plusmn1)...
Summary form only given. The proliferation of system-on-chip (SoC) design has created a whole new market of smart products that have decreased in size while greatly increasing in functionality. However, new challenges have made it more difficult for designers to achieve first-time-right silicon success in time to meet market windows. For designers to be successful, a comprehensive SoC solution package...
Heat generation in one-dimensional structures such as carbon nanotubes and carbon nanofibers (CNF) has raised concerns regarding reliability in these structures under high-current conditions. This paper reports initial efforts to model the effect of heat generation on the I-V characteristics of CNFs. Experimental studies of carbon nanostructures to date have primarily focused on electrical properties...
In this talk, the author give a survey of this important technical field, and also efforts at National Nano Device Laboratories (NDL) for Si-based devices and architectures that maybe implemented along the roads toward 22 nm-node CMOS and beyond for more and more than Moore. In particular, the author deal with some device solutions using Ge or III-V semiconductors for enhancing performance and functionalities,...
Heat dissipation and thermal management of devices package are now a critical problem for applications of high power light emitting diodes (LEDs). In this paper, a novel package method with copper electroplating on the red, green, and blue LED chips were performed. With the copper plating layer, the endurable injection current of these LED chips can be increased easily from typical value of 350 mA...
As device channel length continues to scale beyond 90nm, carrier transport in the ballistic regime becomes critically important. In this paper, the strain engineering and its correlation to the ION current enhancement of CMOS devices in the ballistic regime has been examined. It was characterized by two parameters, the ballistic transport efficiency and the injection velocity. Experimental verifications...
The linearity and link gain performance of analog fiber-optic links based on electroabsorption modulators operating at high optical power is analyzed. The negative feedback attributed to the photocurrent generation improves the modulator linearity at high optical power while causes the link gain to saturate. Potential schemes to improve both will be presented.
The state-of-the-art Intel Core 2 processors has benefited greatly from the utilization of high-dielectric constant (high-k) dielectric film with significant reduction in power dissipation and enhancement in operation speed when compared to Pentium 4. The use of thick high-k material in the advanced CMOS technology has significantly reduced the gate leakage current by avoiding the direct tunneling...
By taking advantages of small contact area of conductive atomic force microscopy (CAFM) and the powerful measurement capability of Agilent 4156C, we applied nano-scaled stresses to oxide samples and measured their breakdown characteristics. We report in this paper the application of nano-scaled stresses to thin gate oxide through CAFM probe tip for gate oxide reliability study including the post-breakdown...
Summary form only given. Recently, there are many interests on electronics nano-device applications based on carbon nano-tubes (CNT). We have studied the low temperature transport properties due to the crossing of two multi walled carbon nano-tubes (MWNTs). Especially, there exists a peak structure in the zero bias anomalies of the I-V characteristics of the crossing and this is found to be very sensitive...
This invited paper reviews the work done in our laboratory on the fabrication of silicon-on-insulator (SOI) materials using plasma hydrogenation and the synthesis of novel silicon-on-diamond and silicon-on-dual-insulator SOI structures with better thermal properties.
This paper presents four topics for low- noise, low-power applications, namely microwave noise characterization, designs of low-noise amplifiers and low-power mixers, and phase noise modeling for oscillators. In noise characterization, we demonstrate that an improper impedance selection can result in 5% uncertainty in the measured noise parameters. For low-power applications, an input matching with...
The modeling of ESD devices, such as MOS transistors, under ESD stress and bias conditions is reviewed. A practical macro-modeling approach composed of industry standard BJT and MOS compact models is presented. SPICE-type circuit level simulations that uses these models is demonstrated. These include examples at both the I/O cell as well as full-chip levels. Predicting ESD circuit performance as well...
This paper reports an analytical drain current model of double-gate (DG) fully-depleted (FD) SOI NMOS devices with the n+/p+ poly top/ bottom gate considering the threshold/ transition voltage effects. Via a comprehensive current conduction mechanism model, the analytical drain current model considering the threshold/transition voltage effects could provide an accurate prediction of performance the...
A simple and efficient strained engineering was reported, by implementing a notch-gate into high tensile-stress CESL (contact etch stop layer) process. Low process changes were utilized to modulate channel stress and implant profile for generating enhanced performance without any extra process step needed. Compared to conventional vertical-gate CMOSFET with an additional offset spacer, device with...
The paper describes a stacked-FinCMOS technology to form high density 3D integrated circuits with local clusters. Circuit design with the described process can utilize the mature 2D design methodology and software with minimal modifications. Standard cells and other building blocks have been designed with the stacked-FinCMOS technology. Preliminary results show that the described process can effectively...
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