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In 3D-IC packages, the Si-to-Si stacking is joint by u-bump which has fine gap structure and high bump count. Because of the high density structure, the flux clean process face challenges. So, non-clean flux is another alternative. However, the flux residue can cause reliability issue such as UF delamination, corrosive relation, electro-migration due to the residue from flux. To reduce the flux residue...
Micro bump interconnect with through-silicon via (TSV) is one of the critical issues for realizing three dimensional (3D) packages. This enabling technology provides more I/O in shrunken die area, and hence high density interconnection. Electroless Ni immersion Au (ENIG), electroless Ni electroless Pd immersion Au (ENEPIG), and plating Tin are commonly used surface finish for Cu pad in lead-free package...
Three dimensional (3D) stacking technology has been purposed to meet miniaturization trend, high performance, and multi-function electronic products. Chip stacking with through silicon via (TSV) and high density lead free interconnection are believed to realize 3D stacking package. Due to the narrow dispensing request for multi-chip connection, non-conductive paste (NCP) is one of the solutions to...
Conventional wafer dicing technology used on one side RDL structure of normal wafer is performed by blade dicing. Nowadays, it applies to through silicon via (TSV) wafer with double side RDL structure which emerges to serve a wide range of 3DIC applications that demands higher levels of performance and heterogeneity integration. However, the phenomenon of severe back-side chipping (BSC) occurs on...
In semiconductor assembly, destructive cross-section observation is the mainstream of defects analysis method, the issues that are making destructive analytical methods to be changed are more tedious and time consuming, because it might cause higher risk of creating artifacts. Nevertheless, advanced 3D x-ray technology enables to substitute the destructive analysis and provides the non-destructive...
An integrated passive device (IPD) solution is one of the important implementation employing the advanced redistribution layers (RDL) technology to fabricate the design passive components. This paper would demonstrate DCS (GSM-1800) Band low pass filter design by using RDL technology. For the design requirement, the specification of insertion loss (EL) of LPF was required bigger than -0.8 dB, return...
Because of the miniaturization on the demand, the area for the layout design is decreasing. But, more and more functions are integrated. In this situation, high-speed design, for example, the DDR access interface is easy to cause simultaneous switching noises (SSN). In this paper, some analysis on this design was evaluated. The major target in our works is the DDR interface. We studied some patterns...
With the need for more functionality, smaller form factor and lower cost products in electronic industry, the various structures of multi-chip 3D packages have become more and more popular. Compared to single die package, the multiple chips package can accommodate with multi-functional devices and increase the memory capacity with. in. same footprints as a single die package. However, such high performance...
The technique of wafer level chip scale package (WLCSP) is similar as flip chip packages without using underfill. The weakest point is solder joint reliability issue so the package size of WLCSP in current industry is used less than 10times10 mm2. In this paper, we use 5.5times5.5 mm2 package size to take as test vehicle and focus on ball peeling and shear stresses to assume and simulate drop test...
In this paper, we study three types of the interconnection between die and die for system-in-package (SIP). The first is the two-dimensional system-in-package (2-D SIP) which is side-by-side dies with wire bonding interconnection. The second is the three-dimensional system-in-package (3-D SIP) which stacks up two dies with wire bonding interconnection and the third is 3-D SIP with TSV interconnection...
System in Package(SiP) includes technologies of Multi-chip Module(MCM), Multi-chip Package(MCP), stacked die, Package on Package(PoP), Package in Package(PiP) and Embedded substrate. While Au wire bonding technology is commonly used as current SIP interconnection solution, take Staked Die structure for example, with increasing stack die number upper die needs longer wire bonding length for signal...
The electronic package warpage is induced by the mismatch of coefficient of thermal expansion (CTE) between different materials that compose the package after specific temperature change process. To well control package warpage after assembly process is an important assignment for packaging engineer because those packages with excessive warpage will be rejected by customers due to board SMT process...
For the high speed substrate design, the synchronization of the signals is one of the most important concerns. Time delay control methodologies that are based on high speed substrate design rules which include equalizing differences between the same group high speed transmission lines, maximizing time balance between different high speed transmission lines and balancing over all nets difference between...
Memory is widely used in most applications. It has the trend for larger storage and higher speed operation, but lower prices. Leadframe based package is a low cost solution for memory applications, but it always has the problem of high lead inductance. Higher power and ground pins inductance design will result in big bouncing noise and make products malfunction. Therefore, how to reduce the lead inductance...
With electronic package tends to be lighter, thinner and smaller, the design of multi-chip become more and more popular. Howev'er, multi-chip in a package also represents multiple heat sources that will result in high thermal dissipation and new technology is required to remove the heat effectively. The 3D stacked package with Through Silicon Via (TSV) technology is developed for chip to chip stacking...
In recent years, miniaturization, lightening, high performance, high reliability and low cost have been demanded intensely for electronic products, especially in the rapid growth of portable cell phone domain. Furthermore, multiple functional demand induces advanced package developments, such as system-on-chip (SoC) and system-in-package (SiP). System-on-chip (SoC) is an ideal package to integrate...
In recent years, miniaturization, lightening, high performance, high reliability and low cost have been demanded intensely for electronic products, especially in the rapid growth of portable cell phone domain. Furthermore, multiple functional demand induces advanced package developments, such as system-on-chip (SoC) and system-in-package (SiP). System-on-chip (SoC) is an ideal package to integrate...
For the high speed substrate design, the impacts of common mode are more and more remarkable, but many designers only consider how to improve a differential mode electrical performance. In the high speed applications, some specifications have defined the standard for common mode performance. In the FCBGA substrates, the capacitance value is quite big near a bumping pad, it causes common mode noise...
With electronic package tends to be lighter, thinner and smaller, Chip scale packages (CSP) become more and more popular for portable electronic products like notebooks, mobile phones, PDAs, digital cameras, etc. For CSP, the die size occupied 80% or above of the package size, so the package profile can be as small as possible to possess better electrical performance dues to shorter interconnections...
The electronic package warpage is induced by the mismatch of coefficient of thermal expansion (CTE) between different materials that compose the package after specific temperature change process. To well control package warpage after assembly process is an important assignment for packaging engineer because those packages with excessive warpage will be rejected by customers due to board SMT process...
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