The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
We have developed a new 3-dimensional (3D) Wafer-to-Wafer stacking technology in which each wafer was stacked one after another, using a unique Through Silicon Via (TSV) fabricated by wet etching technology and surface-micro bump on the lower wafer. Our Wafer-to-Wafer stacking method use a direct connection between backside TSVs of an upper wafer and micro-bumps of a lower wafer. This interconnection...
To reduce the thermal stresses generated in COB interconnection using NCF and flip-chip metallic bumps in conventional high-temperature processes, a surface activated bonding method is used in this study. The bonding feasibility is confirmed at 100-150degC in ambient air using Ar-RF plasma pretreatment under low vacuum. The surface conditions before and after activation are analyzed by X-ray photoelectron...
Flip chip technology is now being introduced in PoP(Package on Package) packages for the digital consumer electronics such as digital still cameras and mobile phones. PoP reduces the component height and improves the electrical performance. A MPS-C2(Metal Post Solder Chip Connection) method was developed for ultrafine pitch flip chip interconnections in mobile applications. A bare die with Sn/Ag-solder-capped...
The impact of Chip-Package Interaction (CPI) which is caused by the mismatch in the coefficient of thermal expansion (CTE) between substrate and chip in a Flip Chip Ball Grid Array (FCBGA) on the mechanical reliability of Cu/Ultra low-k in a larger die was investigated using Finite Element Analysis (FEA). In order to associate the deformation and thermal stresses in FCBGA with those in the Cu/Ultra...
In data transmission equipment for a broadband system, high-speed serial signal transmission has become essential technology. In order to transmit high-speed serial signals with low bit-error-rate, high accuracy in impedance matching of the transmission path is needed. In this paper, first we clarify the relation between the impedance deviations of each part in a signal transmission path and the return...
The following topics were dealt with: advanced packaging; thermal design; mechanical design; signal and power integrity; flip chip and interconnection; advanced material; embedded device; integrated passive device; and 3-D packaging.
In order to realize power supply method with less current/voltage fluctuation, new wiring technology using power supply/ground paired transmission lines with low characteristic impedance (Zo) is propose, and its possibility is examined. This new technology is based on the concept of ldquometamaterialrdquo, and is expected that Zo of the transmission lines will decrease to less than several ohms by...
The recent requirements for achieving higher memory density in a smaller package size have adopted 3D packaging of thin dies in a single package. However, increasing the number of dies in 3D stacking is limited by increasing the cost due to decrease die stacking yield. The known good package stacking can be solution to overcome such yield loss. In this study, a novel Fan-in PoP solution proposed,...
This paper describes the design, modeling, simulation, and fabrication of wafer level integrated passive devices (IPDs). These IPDs, comprising of a resistor, capacitor, and inductor, have been developed in the thin-film and thick metallization processing technology on silicon or high-resisitivity substrate. The electrical equivalent model of the single component structures is presented for design...
The technique of wafer level chip scale package (WLCSP) is similar as flip chip packages without using underfill. The weakest point is solder joint reliability issue so the package size of WLCSP in current industry is used less than 10times10 mm2. In this paper, we use 5.5times5.5 mm2 package size to take as test vehicle and focus on ball peeling and shear stresses to assume and simulate drop test...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.