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During last couple years, Flip Chip package form factor provide the ideal solution for high I/O and better electrical performance on handheld/networking market which included high frequency and high speed product characterization. With developing the fine pitch in chip attach process, there is a methodology called thermal compression bonding combining with capillary underfill (TCB+UF) technology,...
The semiconductor assembly industry has migrated from Au wire to a low-cost alternative, Cu wire, and has recently started increasing the use of Ag alloy wire [1]. Au wire had long been the standard for manufacturability and reliability but increasing raw material costs has shifted the industry to use Pd-coated Cu (PCC) wire as a new standard. Its use is often seen in the industry's latest fine-pitch...
Die attach process play an important role for flip chip packaging. The main factors of die attach yield are: process parameter and flux activity. Die attach flux's main function is to promote good wetting during reflow by removing oxidant and pollutants on pad during flux activation stage. Flip Chip package reliability depends on good bump wetting. Therefore, flux has a significant impact on the reliability...
In recent years mobile devices are getting more and more involved in to our daily life. With the requirement of IC packages inside mobile devices toward smaller form factor, low cost with high performance, a coreless substrate technology, naming Embedded Trace Substrate (ETS) is developed to meet market requirement and it has been studied in this paper. For an IC package with coreless substrate, warpage...
During last couple years, the market of IC package have successful to implement Cu Pillar Flip Chip Technology as a mainstream of high density flip chip solution in each of portable markets(mobile phone, tablet & lots of portable entertainment solution). Moreover, concerning about high end product application which required 10∗10mm above die area on larger flip chip ball grid array product, the...
The development of a thinner core (:5100um) laminate array based exposed die fcCSP package with package to die area ratio > 12, package total height maximum 0.77mm that meets the JEDEC < ±100um warpage requirement is discussed. The same approach used for the 150um thick core exposed die fcCSP technology was used for this work, namely finite element modeling to guide the choice of mold compound...
By employing the physical characteristics of creep deformation mechanisms for solder joints in a flip-chip ball grid array (FCBGA) package under a thermal cyclic condition, an analytical model for the prediction of mean-time-to-crack (MTTC) is presented in the paper. With the consideration of time-dependent thermal testing functionals, the basic co-analyses of one-cycle Nabarro-Herring and Coble creep...
It is well-known that thick substrate core has obviously increased package thickness and also weakened device performance, including electrical and thermal points of view. Therefore, as a NEW innovative coreless structure, a substrate with the features of lead-frame with pre-molding compound techniques has aroused lots of attention in IC semiconductor industry. It has brought not only thin package...
The development of a 2L overmolded exposed die flip chip package is summarized in this paper. The development consisted of first completing extensive thermal & mechanical modeling for optimized package thermal & warpage performance. The modeling results were used to define manufacturing requirements including the bill of materials. Because the die were exposed, a process and BOM that balanced...
Recently, people are seeking lighting source which has higher efficiency and no pollution. Light Emitting Diode (LED) has become important illumination technology for many types of applications. It also has been used in many applications such as watches, indicator lights for many common household devices. LED brought the brightness. In addition, it's eco-friendly to the environment. However, LED's...
With the trend of microelectronics packaging toward more functionality, high performance and smaller form factor, the product is required to deliver more I/Os and better electrical characteristics under a minimum module system. Therefore, a 3D IC integration System in Package (SiP) with passive Through Silicon Via (TSV) interposer technology is proposed to provide high density and heterogeneous integration...
With the quick development of electronic products, IC chip with more functionalities, higher performance, miniaturization, higher reliability and lower cost have been requested intensely, especially in portable device domain such as cell phone, camera, notebook. Based on that, the electrical product using CSP series such as WLCSP, TFBGA, QFN etc. need further evaluation to meet those requirements.
The requirement of Chip Scale Package (CSP) is growing popular in current 3C industries due to the increasing needs of handheld devices and energy saving. Flip-Chip Chip Scale Package (FCCSP) structure is then designed to meet the small form factor as well as high electrical performance requirements with cost efficiency. The purpose of this study is to evaluate the performance of different kinds of...
In recent years, electronic product have been demanded more functionalities, miniaturization, higher performance, reliability and low cost. Therefore, IC chip is required to deliver more signal I/O and better electrical characteristics under the same package footprint. None-Lead Bump Array (NBA) Chip Scale Structure is then developed to meet those requirements offering better electrical performance,...
Evidence on the relationship between state ownership and performance in China's privatized firms is convex, concave and linear. Hence, the nature of this relationship is not resolved. This study examines this relationship for a larger, more recent sample of 4315 firm year observations of privatized Chinese firms during 1996–2003. Results support the hypothesis of a convex relationship between state...
System in Package(SiP) includes technologies of Multi-chip Module(MCM), Multi-chip Package(MCP), stacked die, Package on Package(PoP), Package in Package(PiP) and Embedded substrate. While Au wire bonding technology is commonly used as current SIP interconnection solution, take Staked Die structure for example, with increasing stack die number upper die needs longer wire bonding length for signal...
With electronic package tends to be lighter, thinner and smaller, the design of multi-chip become more and more popular. Howev'er, multi-chip in a package also represents multiple heat sources that will result in high thermal dissipation and new technology is required to remove the heat effectively. The 3D stacked package with Through Silicon Via (TSV) technology is developed for chip to chip stacking...
In recent years, miniaturization, lightening, high performance, high reliability and low cost have been demanded intensely for electronic products, especially in the rapid growth of portable cell phone domain. Furthermore, multiple functional demand induces advanced package developments, such as system-on-chip (SoC) and system-in-package (SiP). System-on-chip (SoC) is an ideal package to integrate...
In recent years, miniaturization, lightening, high performance, high reliability and low cost have been demanded intensely for electronic products, especially in the rapid growth of portable cell phone domain. Furthermore, multiple functional demand induces advanced package developments, such as system-on-chip (SoC) and system-in-package (SiP). System-on-chip (SoC) is an ideal package to integrate...
With electronic package tends to be lighter, thinner and smaller, Chip scale packages (CSP) become more and more popular for portable electronic products like notebooks, mobile phones, PDAs, digital cameras, etc. For CSP, the die size occupied 80% or above of the package size, so the package profile can be as small as possible to possess better electrical performance dues to shorter interconnections...
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