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Fine pitch interconnection is a key stream to accommodate increased I/O applications. This enabling technology provides more I/O in shrunken die area, and hence high density interconnection. However, the majority of studies are focusing on the solder material and failure mode by using various intermetallic compounds (IMC) formation. In order to improve the reliability of the mirco-interconnects, it...
In recent years, the wafer nodes of semiconductor are getting smaller and narrower. In the view of the development trends in the semiconductor & semiconductor packaging technologies, the higher signal LO pin counts and thinner package are wide-spread applied on consumer electronics products (ex: Smartphone, Tablet devices or Digital cameras) as well as high performance network systems and high-end...
In today's industries, utilizing the SMT capacitor is a mature technology and widely used. But, in the future, the 3D-IC stacking assembly, the SMT capacitor might not suitable for the application in the high-speed and higher frequency range. It is caused by the higher density power assumption in stacked 3D-IC configuration. In this study, we test the PDN performance with two conditions, including...
In semiconductor packaging, wire bonding is the main technology for electrical connections between chip and leadframe or substrate. Gold wire bonding has the advantages of a fast bonding process, excellent electrical property and stable chemical property. It has been widely used in various electronic packages. Gold prices have been raised significantly over the last few years. Many manufactures have...
With the quick development of electronic products, IC chip with more functionalities, higher performance, miniaturization, higher reliability and lower cost have been requested intensely, especially in portable device domain such as cell phone, camera, notebook. Based on that, the electrical product using CSP series such as WLCSP, TFBGA, QFN etc. need further evaluation to meet those requirements.
In IC, wire bonding is the main technology for electrical connections between chip and leadframe or substrate. Gold wire bonding has the advantages of a fast bonding process, excellent electrical property, and stable chemical property. But, gold prices have risen significantly over the last few years. Many manufactures have been investigating ways to replace the conventional gold wire various new...
System in Package(SiP) includes technologies of Multi-chip Module(MCM), Multi-chip Package(MCP), stacked die, Package on Package(PoP), Package in Package(PiP) and Embedded substrate. While Au wire bonding technology is commonly used as current SIP interconnection solution, take Staked Die structure for example, with increasing stack die number the upper die needs longer wire bonding length for signal...
An integrated passive device (IPD) solution is one of the important implementation employing the advanced redistribution layers (RDL) technology to fabricate the design passive components. This paper would demonstrate DCS (GSM-1800) Band low pass filter design by using RDL technology. For the design requirement, the specification of insertion loss (EL) of LPF was required bigger than -0.8 dB, return...
For the trend of electronic consumer product, more functionalities, high performance, miniaturization, high reliability and low cost have been demanded intensely, especially in the rapid growth of portable cell phone domain. Furthermore, multiple functional demand induces advanced package developments, such as system-on-chip (SoC) and System-in-Package (SiP). System-on-chip (SoC) is an ideal package...
Because of the miniaturization on the demand, the area for the layout design is decreasing. But, more and more functions are integrated. In this situation, high-speed design, for example, the DDR access interface is easy to cause simultaneous switching noises (SSN). In this paper, some analysis on this design was evaluated. The major target in our works is the DDR interface. We studied some patterns...
With the need for more functionality, smaller form factor and lower cost products in electronic industry, the various structures of multi-chip 3D packages have become more and more popular. Compared to single die package, the multiple chips package can accommodate with multi-functional devices and increase the memory capacity with. in. same footprints as a single die package. However, such high performance...
The technique of wafer level chip scale package (WLCSP) is similar as flip chip packages without using underfill. The weakest point is solder joint reliability issue so the package size of WLCSP in current industry is used less than 10times10 mm2. In this paper, we use 5.5times5.5 mm2 package size to take as test vehicle and focus on ball peeling and shear stresses to assume and simulate drop test...
In this paper, we study three types of the interconnection between die and die for system-in-package (SIP). The first is the two-dimensional system-in-package (2-D SIP) which is side-by-side dies with wire bonding interconnection. The second is the three-dimensional system-in-package (3-D SIP) which stacks up two dies with wire bonding interconnection and the third is 3-D SIP with TSV interconnection...
System in Package(SiP) includes technologies of Multi-chip Module(MCM), Multi-chip Package(MCP), stacked die, Package on Package(PoP), Package in Package(PiP) and Embedded substrate. While Au wire bonding technology is commonly used as current SIP interconnection solution, take Staked Die structure for example, with increasing stack die number upper die needs longer wire bonding length for signal...
The electronic package warpage is induced by the mismatch of coefficient of thermal expansion (CTE) between different materials that compose the package after specific temperature change process. To well control package warpage after assembly process is an important assignment for packaging engineer because those packages with excessive warpage will be rejected by customers due to board SMT process...
In this investigation, normal and high speed ball shear test were used to evaluate the solder joint performance. Solder residual fracture mode is always being found in normal ball shear for low strain rate. The strength of solder balls are directly associated with their mechanical property in normal ball shear test. High speed ball shear provide a easier way to judge the solder joint performance at...
For the high speed substrate design, the synchronization of the signals is one of the most important concerns. Time delay control methodologies that are based on high speed substrate design rules which include equalizing differences between the same group high speed transmission lines, maximizing time balance between different high speed transmission lines and balancing over all nets difference between...
Memory is widely used in most applications. It has the trend for larger storage and higher speed operation, but lower prices. Leadframe based package is a low cost solution for memory applications, but it always has the problem of high lead inductance. Higher power and ground pins inductance design will result in big bouncing noise and make products malfunction. Therefore, how to reduce the lead inductance...
The solder bump interconnection is originated by IBM in the early 1960s and Flip chip technology became popular in packaging. Comparing with conventional wire bonding interconnection package method, flip chip interconnection can offer excellent electrical performance, very small chip size packages and high input/output handling capability. Recently, organic substrates have replaced conventional ceramic...
The reliability life of solder joints is a well-known key topic for the electronics industry. Board level temperature cycling test is most common test method and provide an approximate means of relating the results from these performance tests to the reliability solder attachments for the use environments and conditions of electronic assemblies. Recently, due to environmental debates, SnPb solder...
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