The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper investigates the origin of low-frequency noise in Asymmetric Self-Cascode Fully Depleted SOI nMOSFETs biased in linear regime with regards to the variation of gate voltage and the channel doping concentration through experimental results.
This work presents, for the first time, the Low Frequency Noise (LFN) of submicron graded-channel (GC) SOI nMOSFETs as a function of temperature in the range from 300 K up to 500 K. The measured GC SOI devices are from a 150 nm commercial technology from OKI Semiconductors. The results were obtained through experimental measurements in a device with channel length (L) of 240 nm, working in linear...
This work presents, for the first time, an analytical and explicit model for the intrinsic transcapacitances and transconductances of triple-gate Junctionless Nanowire Transistors. The expressions are derived from a surface potential-based charge model and are validated with 3D TCAD numerical simulations.
This paper explores the use of the back gate bias to enhance the analog performance of self-cascode structures composed by 25nm-long UTBB SOI MOSFETs. It is shown, for the first time, that the use of back gate bias can improve the intrinsic voltage gain by 15 dB, making it larger than the one presented by a 50nm-long single device.
This paper deals with the Low-Frequency Noise (LFN) behavior of submicron Graded-Channel SOI nMOSFETs, fabricated in a 150 nm Technology from Oki Semiconductors as a continuation from previous works, looking at the noise sources of these devices. The effects of channel length reduction and gate bias dependence on the LFN of devices biased in linear regime are investigated. The effective trap density...
In this work, the performance of Ultra-Low-Power (ULP) Diodes implemented with Junctionless Nanowire Transistors (JNTs) is presented for the first time. Experimental data of ULP Diodes formed by Junctionless Nanowire CMOS Transistors show that nanowire width, length and doping concentration play an important role in the reverse current of the diodes, affecting the on-off current ratio.
This work reports, for the first time, an analysis of substrate bias on the analog parameters of Junctionless Nanowire Transistors operating as single transistor amplifiers through experimental and simulated data. The study is performed in terms of output conductance, transconductance, open loop voltage gain and transconductance to the drain current ratio. It has been shown that the substrate bias...
This work presented an evaluation of self-cascode association of short-channel junctionless nanowire transistors, by means of experimental results, comparing data of this configuration to single transistors. Even though the self-cascode transistors have shown to reduce de drain current and transconductance level with respect to single device, due to their longer effective channel length, this effect...
The increasing demand for Systems-on-Chip, where digital and analog circuits coexist, drives the necessity of studying the analog properties of ultimate devices. For technological nodes below 22 nm, multi-gate architecture is considered one of the most promisors since the presence of more than one gate improves the gate control on the depletion charge making this kind of structure extremely robust...
The triple-gate MuGFET is nowadays one of the most important contenders for sub 22 nm MOSFET generation due to excellent control of gate on the channel [1]. Additionally to the better control provided by tri-gate structure, the use of controlled mechanical stress is largely used for boosting the carrier mobility. Biaxial strain is more effective for longer and wider devices due to the relaxation of...
This paper aims to analyze the charges density in multiple gates junctionless devices with different dimensions‥ The analysis of the charge densities was done at the center of the silicon film, at the sidewall and at the top interfaces between the silicon and the gate oxide, for devices with different fin width, height and gate oxide tickness. Based on this analisys, the occurrence of corner effects...
An analytical model to calculate the potential at the surface and at the center of silicon layer for long-channel Junctionless transistors is derived and explained the basic details. The analytical model is compared with the numerical solution of the fundamental equations showing the validity of the assumptions considered.
Multi-gate architecture has been considered as one of the most viable alternatives to MOS devices scaling below 22 nm nodes [1] due to its stronger robustness to the short channel effects with respect to planar architectures. In short channel devices, the control of the gate over the channel charges dramatically decreases making the use of planar devices extremely challenging. Despite providing an...
The use of planar MOS devices for the sub-20 nm era has become a great challenge due to the loss of the gate control on the channel charges [1]. Multi-gate architecture provides a better electrostatic control, allowing a higher degree of miniaturization [1]. One of the major drawbacks of either planar or multi-gate extremely short devices is the formation of p-n junctions between source/drain and...
This work presents a study of the influence of mechanical stress on the low frequency noise in planar SOI transistors operating in saturation. Several channel lengths were measured, and the results show a reduction of the low frequency noise for strained devices independent of the channel length, and this reduction is more effective for smaller channel lengths.
This work presented the analog behavior of nMOS Junctionless transistors in the temperature range of 100 K to 473 K investigated by experimental results and simulations. It has been shown that gm,max of JL present a parabolic-like dependence on temperature. On the other hand, the JL gm/IDS is nearly insensitive to temperature variations in the on state, which can be interesting for several analog...
The harmonic distortion (HD) exhibited by unstrained and biaxially strained fin-shaped field-effect transistors operating in saturation as single-transistor amplifiers has been investigated for devices with different channel lengths L and fin widths Wfin. The study has been performed through device characterization, 3-D device simulations, and modeling. Nonlinearity has been evaluated in terms of...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.