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In this paper, an analysis on the thermal profile of Junctionless Nanowire Transistors is made, where self-heating effects are evaluated in devices with a large 4-contact gate, comparing the results with a minimized gate structure device. Tests are performed for different fin widths and fin heights. The analysis is based on three-dimensional simulations. Results showed that the gate structure is impactful...
This paper studies the effective mobility in n- and p-type junctionless nanowire transistors (JNT) with variable fin width from quasi-planar to nanowire devices. JNTs electrical parameters were analyzed and the results show that smaller fin width have higher mobility while the mobility decreases for quasi-planar devices. Simulations were used to analyze the mobility showing that small fin devices...
This paper investigates the origin of low-frequency noise in Asymmetric Self-Cascode Fully Depleted SOI nMOSFETs biased in linear regime with regards to the variation of gate voltage and the channel doping concentration through experimental results.
This work presents, for the first time, the Low Frequency Noise (LFN) of submicron graded-channel (GC) SOI nMOSFETs as a function of temperature in the range from 300 K up to 500 K. The measured GC SOI devices are from a 150 nm commercial technology from OKI Semiconductors. The results were obtained through experimental measurements in a device with channel length (L) of 240 nm, working in linear...
This paper studies the carrier mobility of triple gate SOI nFinFETs, fabricated on standard and rotated substrates, varying the fin width. The effective mobility results were extracted using the Split CV method, where FinFETs fabricated with rotated substrate show a higher maximum mobility than devices fabricated with a standard substrate. The effects of biaxial strain were also analyzed for the maximum...
This work presents, for the first time, an analytical and explicit model for the intrinsic transcapacitances and transconductances of triple-gate Junctionless Nanowire Transistors. The expressions are derived from a surface potential-based charge model and are validated with 3D TCAD numerical simulations.
This paper explores the use of the back gate bias to enhance the analog performance of self-cascode structures composed by 25nm-long UTBB SOI MOSFETs. It is shown, for the first time, that the use of back gate bias can improve the intrinsic voltage gain by 15 dB, making it larger than the one presented by a 50nm-long single device.
This paper compares the performance of Asymmetric Self-Cascode and Graded-Channel SOI nMOSFETs, both proposed to improve the analog performance of fully depleted SOI nMOSFETs. The differences at device level are evaluated and the impact of their application in basic analog circuits, i.e. common-source amplifier, source-follower and common-source current mirror are explored through experimental results.
This paper deals with the Low-Frequency Noise (LFN) behavior of submicron Graded-Channel SOI nMOSFETs, fabricated in a 150 nm Technology from Oki Semiconductors as a continuation from previous works, looking at the noise sources of these devices. The effects of channel length reduction and gate bias dependence on the LFN of devices biased in linear regime are investigated. The effective trap density...
This paper studies the transport parameters of n-type FinFETs extracted using the Y-Function methodology, by comparing their dependence on the fin width and the crystallographic orientation for standard and rotated substrates as well as the influence of biaxial strain. The Y-Function has been applied with a recursive algorithm to improve its accuracy. The results obtained show that the low-field mobility...
In this work, the performance of Ultra-Low-Power (ULP) Diodes implemented with Junctionless Nanowire Transistors (JNTs) is presented for the first time. Experimental data of ULP Diodes formed by Junctionless Nanowire CMOS Transistors show that nanowire width, length and doping concentration play an important role in the reverse current of the diodes, affecting the on-off current ratio.
This work reports, for the first time, an analysis of substrate bias on the analog parameters of Junctionless Nanowire Transistors operating as single transistor amplifiers through experimental and simulated data. The study is performed in terms of output conductance, transconductance, open loop voltage gain and transconductance to the drain current ratio. It has been shown that the substrate bias...
This work presented an evaluation of self-cascode association of short-channel junctionless nanowire transistors, by means of experimental results, comparing data of this configuration to single transistors. Even though the self-cascode transistors have shown to reduce de drain current and transconductance level with respect to single device, due to their longer effective channel length, this effect...
This work assesses the analog performance of Graded-Channel FD SOI nMOSFET transistors regarding the dependence of gate voltage overdrive over the length of lightly doped region which maximizes the intrinsic voltage gain, unit gain frequency and breakdown voltage. It is shown that the optimum length of lightly doped region depends on the target application of GC devices.
The presence of buried oxide electrically isolating the active silicon region to the substrate in SOI devices leads to better performance than the conventional MOSFETs. However, the thermal resistance associated to this buried oxide causes the self-heating effect which degrades the drain current level. This paper aims at analyzing the self-heating effects influence on junctionless nanowire transistors...
This paper aims at analyzing, through two-dimensional numerical simulations and experimental results, the influence of technological parameters downscaling on the analog performance of Graded-Channel FD SOI nMOSFET transistors. Front gate oxide and silicon film thicknesses, channel doping concentration, total channel and lightly doped region lengths have been varied to target the highest intrinsic...
The increasing demand for Systems-on-Chip, where digital and analog circuits coexist, drives the necessity of studying the analog properties of ultimate devices. For technological nodes below 22 nm, multi-gate architecture is considered one of the most promisors since the presence of more than one gate improves the gate control on the depletion charge making this kind of structure extremely robust...
The triple-gate MuGFET is nowadays one of the most important contenders for sub 22 nm MOSFET generation due to excellent control of gate on the channel [1]. Additionally to the better control provided by tri-gate structure, the use of controlled mechanical stress is largely used for boosting the carrier mobility. Biaxial strain is more effective for longer and wider devices due to the relaxation of...
This paper aims to analyze the charges density in multiple gates junctionless devices with different dimensions‥ The analysis of the charge densities was done at the center of the silicon film, at the sidewall and at the top interfaces between the silicon and the gate oxide, for devices with different fin width, height and gate oxide tickness. Based on this analisys, the occurrence of corner effects...
The origin of the low-frequency noise in submicron fully depleted Graded-Channel (GC) SOI MOSFET is investigated in terms of the channel length comparing two different technologies, OKI semiconductors and UCL.
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