The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
While the scaling of MOS transistors is still ongoing, the miniaturization of the DRAM storage capacitor is reaching a critical limit. A promising solution consists of eliminating the capacitor. Instead, the charges can be stored in the floating body of an SOI MOSFET, which is also used to read out the memory states. The floating-body 1T-DRAM takes advantage of floating-body and coupling effects that...
Multi-gate architecture has been considered as one of the most viable alternatives to MOS devices scaling below 22 nm nodes [1] due to its stronger robustness to the short channel effects with respect to planar architectures. In short channel devices, the control of the gate over the channel charges dramatically decreases making the use of planar devices extremely challenging. Despite providing an...
A single transistor 1T-DRAM, also called Floating-Body RAM cell (FBRAM) makes use of the transistor floating body as a charge storage node. Nowadays, it has become of high interest because it overcomes the integration problems associated with the capacitor of the conventional 1T/1C DRAM. In order to improve the retention time and sense margin, the parasitic BJT (Gen2) programming shows the best performance...
Fully Depleted (FD) SOI technology is well known to provide improved analog performance of CMOS transistors [1, 2]. However, FD SOI transistors may suffer from parasitic bipolar effects (PBE) that cause the degradation of the output conductance [3]. The use of cascode transistors with common gate (making a self-cascode — SC topology) has been shown to reduce the output conductance of MOSFETs, while...
Frequency dependent behaviour of MOSFETs arises from self-heating and source-to-drain coupling through the substrate. In this work the output conductance variation with frequency is experimentally investigated in FinFETs with various fin widths. We demonstrate that fin narrowing suppresses the output conductance degradation due to the substrate effect in the high-frequency range such that self-heating...
Performance of a double-gate (DG) FinFET in the cryogenic environment is discussed based on measurements and simulation. It was found that the DG FinFET has an excellent immunity to the kink effect in the cryogenic environment. Our physics-based compact model reproduced the measured I–V characteristics. The successful demonstration of an opamp consisting of the DG FinFETs at 4.2 K is also presented.
The use of planar MOS devices for the sub-20 nm era has become a great challenge due to the loss of the gate control on the channel charges [1]. Multi-gate architecture provides a better electrostatic control, allowing a higher degree of miniaturization [1]. One of the major drawbacks of either planar or multi-gate extremely short devices is the formation of p-n junctions between source/drain and...
The continuous reduction of the devices has driven the scientific community to explore alternative technologies that are compatible with CMOS technology, but with different operating principles. The Tunnel Field Effect Transistors (TFETs) are a new conception of devices that have been proposed as a promising option to replace conventional MOSFETs, since its physical structure allows a very steep subthreshold...
In recent years, CMOS on Silicon-on-Insulator has rapidly evolved as a mainstream technology for switches used in wireless applications. Since such applications can involve switching high power levels (35 dBm) at high frequencies (∼2 GHz), the technology considerations are substantially different than those for SOI used in high speed, small signal applications such as microprocessors. This paper provides...
The Uniformity of SOI layer thickness is need to be within plus or minus 5%, because an increase of dispersion of the silicon layer thickness increases the characteristic variation of fully depleted SOI MOSFETs. The thickness range of the SOI layer is required to be smaller and smaller, since the thickness of the silicon layer keeps getting thinner and thinner with the miniaturization of MOSFETs....
This work presents an unreleased CMOS-integrated MEMS resonators fabricated at the transistor level of IBM's 32SOI technology and realized without the need for any post-processing or packaging. These Resonant Body Transistors (RBTs) are driven capacitively and sensed piezoresistively using an n-channel Field Effect Transistor (nFET). Acoustic Bragg Reflectors (ABRs) are used to localize acoustic vibrations...
We have successfully fabricated InGaAs-OI tri-gate nMOSFETs, for the first time. The devices were depletion-type (p-n junction-less) nFETs with Fin-channel width (Wfin) down to 20 nm and had metal source/drain structures. It was experimentally demonstrated that Wfin scaling effectively improved cut-off properties at Nd up to 5 × 1018 cm−3 and the electron mobility in the narrowest channel (Wfin =...
□ CMP created in 1981 □ Offering industrial quality process lines (University process lines cannot offer a stable yield) □ Design-kits linking CAD and processes, to facilitate the design. □ Customer base development + Universities / Research Labs + Industry + 1000 Institutions in 70 countries □ Non-profit, Non-sponsored.
Silicon on Insulator (SOI) Technologies offer many advantages for the fabrication and advanced packaging of MEMS and IC devices and systems. The buried oxide provides an excellent etch stop and the silicon layers on top can be selected for the exact thickness, crystal orientation, and purity for the required application. These properties are exploited for the fabrication and packaging of MEMS devices...
Variability has become a major concern, forcing the industry to consider new transistor architectures for the 22nm technology generation and below [1]. Fully depleted thin-body transistors with improved electrostatic integrity tolerate an undoped channel promising significant reduction of the random-dopant component of the statistical variability. The implementation of such transistors in future CMOS...
□ The fabless semiconductor industry has provided enourmous innovation and cost reduction over the past 21 years □ The growth in mobile computing and connectivity indicates that semiconductor opportunities will continue to increase □ Power efficiency is a key focus area for SoC designers as they deliver ICs into these market segments □ SOI technology and fully depleted devices have potential to provide...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.