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In this paper, simulation and optimization of a micro flow sensor is presented. Modeling of the micro flow sensor using ANSYS Fluent for temperature distribution is studied. The detailed structure of the micro flow sensor chip is considered in the simulation model. What's more, the temperature dependencies of physical properties of air are defined to improve the model precision. As a key parameter,...
Data communication over Polymer Optical Fibers (POF) is limited to only one channel for data transmission. Therefore the bandwidth is strongly restricted. By using more than one channel, it is possible to break through the limit. This technique is called Wavelength Division Multiplexing (WDM). It uses different wavelengths in the visible spectrum to transmit data parallel over one fiber. Two components...
In this work we demonstrate a new selective metallization technique to perform localized plating on the screen-printed Al contact using the innovative approach based on Dynamic Liquid Drop/Meniscus that is able to touch the cell back contact in specific defined positions and show that it is possible to produce suitable electrical and mechanical contact with Al-Si and thus to replace the silver from...
We studied the effect of substrate with patterned structure on the light extraction efficiency (LEE) of chip-on-board (CoB) packaging light-emitting diodes (LEDs) by optical simulations based on Monte Carlo ray-tracing method. Two kinds of typical patterned substrates were analyzed which were with conical and spherical structure, respectively. Results show that when the encapsulation layer is without...
An adequate sequential etching though dielectrics, silicon and permanent adhesive material was successfully developed for the damascene interconnects in the face-to-back bumpless TSV Wafer on Wafer (WOW) processes. The induced bowing taken place at the etching of permanent adhesive was optimized and no void Cu metallization was achieved. According to those TSV technology, the upper and lower stacked...
Trenches on silicon have found important applications in microelectromechanic system, microfluidic devices, photonic devices, capacitor memory devices and etc. Etching trenches with controllability of 3D geometry receives growing interests from academia as well as industry. In this paper we introduce a novel wet etching method, named metal assisted chemical etching, as a promising trench etching technology...
In this paper, the trimming process in manufacture of a power module is investigated by using the commercial FE code Ansys/LS-dyna®. The setup of the trimming process consists of an automated system of cutting die, stripper, punch, and etc. The design and interworking of these tools are quite critical. On one hand, when the gap between the punch and stripper/cutting die is too big, the dambar may...
We present a cost-efficient and reproducible technique for assembling 3D components to mechanically bendable low glass transition temperature (Tg) polymeric interposers. First, we propose localized soldering using a focused hot air gun. Second, we use eutectic solders, which permit reflow at temperatures close to the Tg of the interposer. Then, we adopt differential heating and cooling in order to...
As a common problem in wafer lever packaging(WLP), wafer warpage caused by heat process should be carefully controlled in case of product inaccuracy or yield loss, and redistribution layer (RDL), as a key structure of WLP, is one of the major concerns that causes warpage. In this paper, a novel RDL tailored by pulsed electrodeposited nanotwinned copper (nt-Cu) was introduced into WLP. It was found...
The recent applications of 3D X-ray computed tomography (CT) in microelectronic packages, including nondestructive failure analysis, defect monitoring in solder joints and Cu vias, and progressive reliability study of solder voids, electron migration induced void nucleation in solder joints, and void evolution in Cu vias are reviewed. The high resolution and non-destructive 3D X-ray CT data has proven...
The industry is going through a transition in material sets for second level interconnects including adoption of leadfree solders. High-rel systems may often have a mix of components with different solder alloys in the printed circuit assemblies including both leaded and leadfree solders because some original leaded components may only be available in leadfree configurations. In this paper, the potential...
Along with the advancement in miniaturizing of mobile devices, typified by smart phones and tablet PCs, the semiconductor PKG substrate installed in these devices is demanded to be thinner and higher in density. As one of the most innovative solutions, the PoP (package on package) technology, which has the three-dimensional construction, has been expanding rapidly in recent years. However, the thinner...
The advance of mobile electronics applications has been demanding higher drop/shock reliability performance under more severe drop/shock impacts. This in turn is requiring the board level reliability (BLR) drop test to be able to reach higher peak acceleration, particularly higher than 5000 G. One method to reach this high acceleration is to use an apparatus called Dual Mass Shock Amplifier (DMSA)...
In this paper, we will describe a new low cost solder bumping technology for use on wafers. The wafer IMS (injection molded solder) process can form fine pitch solder bumps on wafers, while offering greater solder alloy flexibility. This method is also applicable to form uniform solder bump heights when a wafer has different size and shape of I/O pads. The wafer IMS bumping process uses a solder injection...
The ever-increasing demand for higher I/O counts on chip requires the finer pitches to improve the performance, cost effectiveness and higher yield. The conventional under bump metallization (UBM) technology may not guarantee the required performance due to higher current density and diffusivity nowadays. In order to overcome these challenges, a UBM with higher strength and resistance to diffusion,...
e-CPI has emerged as a new risk in modern chip design as silicon dies become increasingly thinner and packages become increasingly more complex. e-CPI is different from traditional mechanical reliability related chip-package interaction, as it focuses on package stress impact on electrical circuit performance. A complete e-CPI modeling flow has been demonstrated. Both package FEA models and silicon...
An experiment is conducted to study failure mechanism during flip chip attach process for Cu Pillar bumped Si device that uses mass reflow assembly technology. A three-leg design of experiment (DOE) is conducted, which includes two UBM sizes, two different Cu pillar height, and with / without polyimide option to collect basic failure information. Finite element software is used to correlate the failure...
This paper reports on the design, fabrication and characterization of active die embedded ultra slim system-in-packages suitable for integrating RF and digital integrated circuits, and discrete components. Portable communication devices such as Ultrabooks, tablets and smart phones require very small form factor radio subsystems. To address this need, several proof of concept (POC) packages with embedded...
This paper reports a perspective investigation of computational modeling of fluid-structure interaction (FSI) in molded integrated-circuit(IC) packaging. The investigation is carried out through two aspects, respectively on interaction between the fluid and structure in the encapsulation process and appropriate methodology for modeling. We present a novel and integrated method to predict the FSI during...
This paper provides the physics of failure (PoF) analysis methodology in a three-dimensional integrated circuit (3D IC) integration based on mechanical and thermo-mechanical concepts. The majority of research on the 3D IC package has focused on the Coefficient Thermal Expansion (CTE) mismatch and heat junctions. The primary problems of CTE mismatch and heat dissipation cause failures or fatigues in...
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