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The applications of 2.5D/3D IC integration have been increasing in recent years, which enable high-density and heterogeneous ICs that can be assembled in one package using through silicon interposer (TSI). In this paper, the integration study of interposer in backside via reveal (BVR) process, various bumping volume and stacking reliability were introduced. Different sizes of solder bump forms on...
A high performance embedded computing module was enabled and demonstrated with the implementation of a 3D Si interposer. The interposer contained front and backside multilevel metallization (MLM) with through-Si vias (TSVs) on 150mm wafers. The front-side MLM (5 levels) was fabricated with a dual damascene process. Four 2 um thick Cu routing layers with 2 um oxide dielectric layers and one pad layer...
This paper reports novel interconnect technologies to enable a large scale ‘interposer tile’ and ‘silicon bridge’ interconnection platform. Microfabricated self-alignment structures enable high alignment accuracy between the components. Mechanically flexible interconnects (MFIs) are utilized to enable rematable electrical interconnects. Moreover, a proof of concept demonstration with interposer tiles...
There is growing interest in applying glass as an interposer substrate for 2.5D/3D as well as component substrates for radio frequency (RF) applications. The list of important advantages provided by glass in these applications include material properties (e.g. electrical performance, ability to adjust coefficient of thermal expansion (CTE) to improve reliability) as well as the significant opportunities...
Large area silicon or glass interposers may exceed the maximum imaging field of step and repeat lithography tools. This paper discusses the lithographic process used to create a large area interposer on a stepper by the combination of multiple subfield exposures. Overlay metrology structures are used to confirm the relative placement of the subfields to construct the interposer. Routing lines from...
An analytical model simulating the bowing at wafer or thin die level was applied to imec's 3D interposer technology. The calibration methodology is explained. A good correlation between simulation and measurement has been found at different stages during the processing. Secondly, a model combining all the interposer features was used to simulate the bowing induced at wafer and thin die level. Finally,...
In this paper, a new TGV interposer technology is introduced in which the through via could be made by using a photolithography and chemical wet-etching. To make fine and accuracy via-holes, etching properties of the glass are studied in various UV-exposure times. It is possible to make TGVs from 60 μm to 20 μm with a 4:1 aspect ratio. Based on the TGV process, a high-aspect-ratio metal is made and...
As device dimension shrinks less than 65nm, the propagation delay, crosstalk noises, and power dissipation due to RC (Resistance Capacitance) coupling becomes significant. Cu and LK (Low-k dielectric) material have been introduced to reduce such delays and allow higher device speed and better performance. However, since dielectric material with low-k value usually possesses large amount of porosity,...
Cu Column bump has seen growing adoption in both high-end and low-cost mobile devices as well as in consumer, computing and networking devices. Higher input/output (I/O) density and very fine pitch requirements are driving very small feature sizes such as small bump on a narrow pad or bump on lead (BOL), while higher performance requirements are driving increased current densities, thus making electromigration...
In this study, electromigration (EM) performance of 60μm pitch Cu pillar bumps assembled with bump on trace (BOT) process by using thermal compression bonding with non-conductive paste (TCNCP) is investigated. Emphasis is placed on the EM experimental measurement and analysis of the Cu pillar bump on trace. The test temperature ranges from 140–160°C and the current of 500–900mA are applied, which...
In this paper, the integration accuracy of conventional flipchip bonding is effectively enhanced by means of automatically maintaining the alignment between the chip and substrate during the time that offsets may take place, i.e., bonding conditions applying period. The conventional bonding bump and pad elements have been appropriately modified to construct a concave-convex pair, i.e., self-aligned...
This paper reports on second-level interconnection development for a large-scale Ball Grid Array (BGA) package. Generally, control of warpage becomes a problem as BGA packages become larger. To solve this problem, the following two measures were executed. The first was adoption of a low-temperature solder, and the second was warpage control using a heat spreader as a fixture. We were able to decrease...
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