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This paper discusses multi-point address channel design in fly-by topology for high speed memory interface. Waveform behaviors at DRAM locations along the channel are examined in depth with eye opening data in various channel design factors and device termination settings. Eye opening is exacerbated on the front DRAM from the controller more prominently due to ring-backs from high frequency reflections...
Voltage supply noise can impact circuit system performance and functionality. FPGA (Field Programmable Gate Arrays) applications vary from different usage model, the detection of supply noise is crucial for these applications. Detection sensitivity is directly related to detector stage delay. This paper discusses the detector stage delay versus sensitivity relationship. It also demonstrates a novel...
In high density, high speed Serdes interconnect designs, inappropriate pin placement can lead to differential crosstalk violation. How to relatively compare the crosstalk level due to various pin placements, and estimate its effect on the whole system without time consuming simulation is critical. This paper introduces a simple method to estimate the relative differential crosstalk due to various...
This paper discusses link routing budget considerations for PCIe Gen3 designs in server systems. Special attention will be given to channel discontinuities and their effect on eye opening. Link training complications will be discussed with respect to equalization and tuning behavior when accommodating multiple transmitters and receivers from different vendor sources. Insertion loss plots and eye simulation...
This paper introduces a novel air-dielectric via structure which can improve the interconnect signal bandwidth by reducing the impedance mismatch in vias of high speed system PCBs carrying 20 Gbps+ signals. Design methods of the proposed air-dielectric structure are presented. Using these methods a system target design impedance can be better matched thus causing reductions in the signal degradation...
This paper discusses the impact of DC wander also called baseline wander resulting from AC-coupling on signal integrity in receive waveforms in AC-coupled serial bus links with focus on PCIe Gen3 signaling. Receive signal behavior from charging and discharging activities of AC-coupling circuit is studied for fundamental understanding of baseline wander and its effect through simulations of short and...
This study presents a dielectric waveguide via design. The design serves two purposes. First, it removes the need for DC-blocking capacitors within a high speed signaling system. This is because it is free of conductors and made of dielectric materials thus inherently accomplishing DC-blocking on a signal travel route. Second, it allows for efficient via performance at millimeter wave frequencies...
As DDR4 continues to move from the design phase towards implementation, several challenges have been identified to successfully implement this high performance memory architecture for next generation systems. This paper investigates driver design selection for DDR4 systems. The paper studies the pros and cons of three driver design types namely: standard, pre-emphasis, and de-emphasis on typical net...
This paper discusses electrical performance and design aspects of SAS (Serial Attached SCSI) link channels in various server storage system configurations through modeling and simulation analysis in frequency and time domain. The signal loss behaviors are investigated in two interconnect structures, internal SAS links in host enclosure backplanes and external SAS links in cabling environment. While...
The continuous increase in microprocessor performance demands an equal order of increase in the bandwidth requirements on the memory and I/O interfaces. Providing the required bandwidth at an acceptable cost is a challenge to the system packaging engineer. This paper discusses how a passive channel can be optimized in a cost effective way to provide the maximum bandwidth. The paper focuses on the...
High performance glass ceramic (HPGC) packages widely used in various range of IBM server applications are characterized for high frequency performance of SerDes differential links using TDR and network analyzer measurements and their design to performance aspects are analyzed in depth. Also HPGCspsila merits and design to electrical factors are discussed in comparison with an Alumina Ceramic and...
The need for radio frequency (RF) test at the wafer level in high-volume production has increased in response to the growing demand for delivering complex "good known dies" (KGD). To keep pace with the market, innovative test solutions need to be developed to meet tighter electrical specifications while maximizing yields and profit margins. This paper presents a versatile test platform built...
This paper discusses a package design technique to enhance high speed signal performance by reducing the large discontinuity effects at the vias and solder ball interfaces. In the technique, an intentional counter-discontinuity in complementary phase to existing discontinuity is inserted to mitigate the existing discontinuity. Transmission line behavior of short multiple discontinuities are analyzed...
This paper discusses the challenges in balancing the wireability, performance, and cost of low cost wirebond packaging for high speed SerDes applications in application specific integrated circuits (ASICs). In-depth analysis was performed using 3D electromagnetic simulation to evaluate the effect on performance of various design factors along the signal path of the wirebond package, including bondwire,...
This paper discusses the trade-offs in performance and cost of high speed SerDes in wirebond package applications. While many protocol standards specify requirements for both common mode return loss and differential mode return loss, meeting both sets of requirements in low cost wirebond packages requires the designer to make significant trade-offs. The performance and cost impacts of improving common...
This paper discusses a new efficient monitoring method for impedance control using statistical impedance distribution generated from physical dimension data on line shape which are collected from manufactured products. In the method, statistical analysis is conducted on physical dimensions using randomly generated simulation data based on manufacturers' data, as well as measured data to predict potential...
This paper discusses design tradeoffs for high speed signal performance in buildup laminate packages with high wiring density. Trace design in die escaping area, PTH vias placement pattern and BGA I/O assignments are analyzed in depth for design optimization through numerous simulations as major areas of high coupling concern and channel performance. Then design suggestions are made at each area for...
The water level control system of the steam generator in a pressurized water reactor and its control problems are analysed. In this work, a stable control strategy during low power operation and transient states is studied. The control strategy employs substitutional information using the bypass valve opening instead of incorrectly measured signal at the low flow rate as the fuzzy variable of the...
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