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The intricacy in the manufacturing of MEMS devices has resulted in decreasing parametric yields. The problem of reduced parametric yield is increasing with the waning feature sizes. The necessity for yield enhancement in MEMS designs and particularly in commercial MEMS is being increasingly felt by the industry and therefore by the designers. There has been no standard methodology that could be followed...
We have developed a low cost 1.25 Gbps WDM bidirectional module using two integrated optical subassemblies which are composed of a planar lightwave circuit (PLC) platform and a silicon optical bench (SiOB) platform. The low cost module is achieved by employing a flip-chip bonding method with passive alignment using a Fabry-Perot laser diode (FP-LD) with a monitoring waveguide-photodiode (PD) on a...
There is an increasing demand for portable, reliable, and cost effective bioelectronic systems for applications ranging from clinical diagnosis to homeland security. Conventional detection systems involve labeling the probe molecules, large amount of target molecules to enable detection, and elaborate signal transduction methods. Most of them also have to couple with optical detection equipments that...
A large scattering of creep data of Pb-free solders existing in literature was investigated by conducting controlled experiments using Sn-3.5Ag alloy. Tensile specimens with different solidification rate from the melt were prepared to study the effect of solder microstructure, while simple shear (SS) and lap shear (LS) tests were added to find a mechanistic effect of multiaxial loading. Effects of...
This study is confirmed and provided a reliable solder joint reliability about Ni UBM/penetration layer/SnAg lead-free solder bump structure for mobile application. Investigated of the mechanical strength and evaluated with ball shear test the Ni UBM/penetration layer/SnAg lead-free solder bump structure after 10 times multi reflow test, isothermal aging at 150?C for 1000 hours and thermal cycling...
A System Design-for-Reliability (SDfR) is a method for designing subsystems, selecting components, and designing interconnections to achieve targeted system reliability in a given context. This paper presents SDfR Tools based on Reliability Object Model (ROM) that provides a framework for System-Design-for-Reliability of next generation highly integrated electronic systems. The SDfR tools developed...
The delamination at the copper lead frame and the epoxy interface adversely affects the reliability of IC packages and this is a common failure mode during the qualification process. One of the factors governing the interfacial delamination is the moisture content at the interface. This study further developed the experimental measurement of interfacial moisture diffusion by Fourier Transform Infrared...
The size of IC device has been reduced resulting from the reduction of both transistor gate length and bond pad pitch. Since 180 nm node, wafer fab technology has decreased the gate length more aggressively than the assembly site does with bond pad pitch. Both bond over active (BOA) and fine pitch wirebonding have been implemented simultaneously in order to minimize the white space area in the die...
Warpage of flip chip package is mainly dominated by the substrate stack-up. Mismatch by coefficient of thermal expansion (CTE) and Young's modulus (E) in package materials should be responsible to this phenomenon. Also, glass transition temperature of polymeric materials such as solder mask and dielectric dominate the warping direction. In general, the substrate is modeled as a bulk material composed...
Out-of-plane displacement (warpage) has been a major reliability concern for board-level electronic packaging. Printed wiring board (PWB) and component warpage results from CTE mismatch among the materials that make up the PWB assembly (PWBA). Warpage occurring during surface-mount reflow process and normal operations may lead to serious reliability problems. PWB/PWBA warpage can be measured by many...
Signal integrity (SI) and cross-talk concerns play significant roles constraining design options for low-cost, high speed interconnect solutions. The electrical packaging and signal integrity engineers must focus on SI and noise concerns even though the cost pressure continues to drive for the use of lower cost packaging along with increased overall function. Target cost trends have caused designers...
This paper described the shadow moir? measurement of bare flip chip coreless and standard (3/2/3) BGA substrate to inspect the change of each thermal history (0hr, after prebaking, IR-reflow), the warpage increased significantly on IR reflow peak temperature and largest warpage located around the C4 area of coreless FCBGA substrate and standard FCBGA substrate change was not obvious. Electrical performance...
Telecommunication equipment that supports high-level information networks is being made portable, small and lightweight. Thus, the miniaturization of semiconductor devices is necessary, and chip thinning and flip chip technologies are key in achieving it. The typical flip chip manufacturing steps for thin semiconductor devices are as follows. First, semiconductor elements are formed on a wafer. Surface...
The compatibility of lead-free area array packages with tin-lead soldering processes is a critical issue, as several product categories may take advantage of the exemptions under the European Union (EU) RoHS legislation and continue to be built with tin-lead solder for some time to come, whereas the components have become predominantly lead-free. The issue of "backward compatibility" arises...
An overview of important pattern density requirements and tradeoffs for advanced RF, analog and digital technologies is presented. This paper reviews process sensitivities to pattern density, the advantage of pattern density compliant designs, performance and modeling considerations, and presents methods of detecting and enhancing pattern density deficiencies to improve overall manufacturability.
Ink jet printing of self-assembled monolayers (SAMs) on copper provides a potential route to the digital manufacture of patterned tracks and micro-fabricated devices. However, forming a SAM layer using conventional solution methods is challenging due to the native oxide layer on copper, and this issue is magnified for ink-jet printing, where the oxide layer must be removed, without rendering the substrate...
The migration to lead free connections in the microelectronic industry has brought forth many technical challenges, especially in the packaging technology area with respect to materials and processes. The two major drivers to these challenges are the higher melting point and the thermo-mechanical behaviour (less creep than SnPb alloy) of the replacement alloy. The higher melting point drives higher...
A comprehensive study was undertaken to evaluate various board design parameters, assembly and reliability of 0201's as it relates to high reliability products. The design parameters considered included four pad designs, two trace width terminations, three orientations, three board thicknesses and four component to component spacing on a large PWB panel. The assembly parameter evaluation included,...
Passive UHF (Ultra High Frequency) RFID (Radio Frequency Identification) is a promising technology for products tracking in logistics or routing packages in supply chain. However, the RFID tag is significantly affected by objects surround it especially metallic objects. In this paper, we disclosed a new method using electromagnetic band gap (EBG) material to insulate the UHF RFID tag from backside...
Continued miniaturization, increased performance, as well as increased reliability of microelectronics require development of new design and manufacturing methods. Embedding discrete passive components into the substrate has been identified as a solution capable of accommodating a portion of the future demands on microelectronics. As embedded passive components are fundamentally different from discrete...
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