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The co-design of a 10Gb/s 45nm CMOS transceiver and low-loss interconnect for parallel links demonstrates 1.4–2.4pJ/bit I/O power efficiency. A C4 bump pattern with an effective 20∶3 signal to ground ratio is implemented with on-die transmission line routing to escape from the I/O circuitry to the package-die interface. Top-of-the-package connector based (TPCB) interconnects, including high density...
A new equalized on-chip global link structure is proposed for ultra-high-speed and low-energy communication by utilizing continuous-time linear equalizer (CTLE). Modeling and optimization approaches for each building block are introduced and a low-power driver-receiver co-design methodology is proposed to greatly reduce energy-per-bit by 50%. Final design can achieve 20Gbps signaling over 10mm, 2...
Memory power consumption has become a main driving force of new memory technologies. Low voltage DDR3 (DDR3L) has emerged to provide optimal solution for performance and power for certain market segments. With empirical data, this paper demonstrates the scaling of DDR3L signal integrity performance and power consumption at full system level. The signal integrity performance is degraded by 10∼20% in...
Conventional current-mode summation utilized in feed-forward equalization (FFE) has disadvantages in power consumption and linearity and thus becomes less attractive when high-speed low-power equalization is required. A Multi-Capacitor (MultiCap) structure is presented to overcome these disadvantages by supporting voltage-mode summation. This passive structure replaces the current-summation block...
An I/O design framework is presented which combines statistical link analysis with circuit power models to predict the power-optimum equalization architecture, circuit style, and transmit swing at a given data rate, channel, and process node.
In high-speed chip-to-chip single-ended signaling links, far-end crosstalk presents one of the dominant noise sources, limiting the link performance. Diagonalizing the channel using modal decomposition has been proposed to mitigate the crosstalk, but so far only the application to uniform low-loss transmission line channels has been investigated. In this paper, application of modal decomposition to...
This paper describes a system-level signal integrity analysis of bus turn-around for a DDR3 SDRAM [1] implementation supporting 3 DIMMs per channel operating at speeds up to 1333MT/s with dynamic on-die termination (ODT). The method provides facilities for arbitrary DIMM population and ordering, noise modeling within a data group, network excitation including dynamically controlled ODT timing, and...
In this work, the polyharmonic distortion (PHD) model is used to analyze the behavior of high-speed nonlinear links. The model assumes the validity of the harmonic superposition principle for high-speed I/O links. From the PHD formalism, a frequency-domain X-parameter matrix formulation is derived. The formulation accommodates both port and harmonic dependence of the signals. Relationships are derived...
Multi-physics modeling offers rich opportunities for studying the properties of through-silicon vias (TSV). Results of a TSV study with the theories of electromagnetics, semiconductor physics, and thermal physics are presented. Equivalent circuit models are used to draw together the three different theories to perform the TSV modeling. Moreover, a single TSV is examined for high-speed signal transmission...
3D integration is expected to lead to a semiconductor industry paradigm shift due to its tremendous benefits to performance, data bandwidth, functionality, heterogeneous integration, power and cost. In this work, we consider the case where solder balls and through-strata-vias (TSVs) are paired to electrically connect stacked chips in a vertical fashion. For the given solder-TSV configurations, transient...
In today's integrated circuits, power consumption has become the most important factor, and must be seriously investigated among the various performance metrics. In this study, power estimations for various through-silicon via (TSV)-based three-dimensional integrated circuit (3D IC) designs were conducted in efforts to realize low-power-consumption 3D IC. In addition, the dominant power-consuming...
A resistance and capacitance (RC) passive equalizer is proposed to improve the eye diagram of a through silicon via (TSV) in this paper. To begin with, an analytical circuit model of the TSV is derived by using the transmission line theory, and based on which, the simplified circuit model is obtained. It is shown that the insertion loss of the TSV from DC to several GHz mainly depends on the capacitance...
SSO noise modeling imposes significant challenges in signal integrity analysis as it requires a complex model which represents numerous signal, power, and ground conductors and planes. Even with effective macros modeling techniques, the resulting model is still complex due to a large number of external nodes which often represent data, power, and ground pins or pads. This paper discusses several options...
This paper proposes a simulation methodology to quantify the relative impact to the maximum CPU core operating frequency, also known as Fmax, for different power-delivery network designs. Good measurement-simulation correlation for designs with different decoupling capacitance has been presented to validate the proposed technique. Through careful consideration of the process, voltage, and temperature...
This paper discusses the electrical characteristics of power distribution networks (PDNs) in 3DICs on both system and chip level. In the system-level analysis the global resonance effects in 3D PDNs are highlighted. For chip-level analysis, detailed metal-layer-based power grid model is proposed for the first time for 3D PDNs. With the detailed power grid model, local resonance effects that are unique...
In this paper, we propose a novel design of embedded filter for the noise decoupling between power and ground planes. At its isolation band, this compact filter provides a short path for the return current of the signal. Therefore, it prevents the propagation of the digital switching noise along the power distribution network, and improves the power integrity. This embedded filter provides the noise...
New algorithms are needed to solve electromagnetic problems using today's widely available parallel processors. In this paper, we show that applying the optimized waveform relaxation approach to a partial element equivalent circuit will yield a powerful technique for solving electromagnetic problems with the potential for a large number of parallel processor nodes.
It has been observed that a finite-element based solution of full-wave Maxwell's equations breaks down at low frequencies. Existing approaches have not rigorously solved the problem yet since they rely on low-frequency approximations. Moreover, little work has been reported for overcoming the low-frequency breakdown for realistic circuit problems in which dielectrics and non-ideal conductors coexist...
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