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In this paper, the the authors summarise Sn/Ag Pb-free plated bumps that have been qualified for low-k 65 nm technology on thin-core build-up laminates. The bump pitch is 200 mum, and the laminate size is 42.5 mm. One of the key issues addressed in this qualification was whether Pb-free bumps along with assembly to build-up laminates with thin-core result in enough stress to cause any low-k related...
A thin flip-chip (FC) BGA with a 65 nm device has been developed for the bottom package of package on package (PoP) packaging for mobile equipment. The device has a low-k interlayer dielectric (ILD) that is known to be fragile material, and the device and the substrate are connected by lead-free solder bumps in taking environmental safeguards into account. The bumps are arranged in 120 um pitch staggered...
Microelectronic packaging continues the migration from wire bond to flip chip first level interconnect (FLI) to meet aggressive requirements for improved electrical performance, reduced size and weight. The interconnect pitch is being predicted by forecasts like ITRS to be reduced to 100 um and below for full array I/O layout. For wafer bumping, solder electroplating is commonly employed, especially...
Advanced silicon node is becoming the mainstream technology used for electronic product and flip chip package is one of the assembly solutions to meet of high-end products requirement. For flip-chip assembly application, reducing the core thickness of substrate to derive higher electrical performance and routing density has been approached. Combining with lower mechanical strength characteristics...
Technology migration of the Cell Broadband Enginetrade (BE) Microprocessor to 65 nm chip technology precipitated a redesign of the original IC packaging. While many of the design changes were necessitated by the chip technology migration, other modifications were implemented to enhance the robustness and overall manufacturability of the product. This paper will discuss key aspects of the 65nm chip...
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