The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The following topics are dealt with: electronic packaging; low power design; fine pitch technology; connectors; distorted serial systems; jitter; amplification; capacitance measurement; dielectric constant; dielectric loss tangent; impedance measurement; power supply system; current measurement; power distribution networks; noise suppression; switching noise; power plane noise; mixed signal systems;...
In the last few years, power and power delivery have become the major concerns to computing platforms. The emphasis on power led to several fundamental changes in the design approach of high performance microprocessors. The most notable and visible change was the move to more energy efficient architectures such as the multi-cores. Less visible but equally important changes were also achieved at the...
I/O power represents a sizeable portion of the overall power budget on a low power mobile platform. Significant fraction of that I/O power is used to ensure signal integrity on the high speed buses. While there is flexibility to trade off I/O power consumption against signal quality on Intel's current mobile and sub-note platforms, inefficiency still exists on wide I/O buses such as FSB and DDR2....
We demonstrate multi-Gbps pulse signaling with 100um diameter coupled inductors across a substrate to substrate interface. This has application in realizing sub-mm pitch surface mount zero insertion force (ZIF) connector interconnect structures
This paper introduces high-speed packaging designers to a broadly adaptable performance assessment tool designed to establish and demonstrate the operating margin of channels and channel features in 10 Gb/s serial systems. An interactive hardware tool is described that enables comparison of reference channel performance with that of selectively degraded channels and associated channel construction...
Jitter amplification characteristics of different forwarded clock channels at 6.4 and 9.6 Gb/s are illustrated with model correlations. The effect illustrates the need for quarter rate clocking at higher speed, in lossy serial links
This paper describes a technique for characterizing on-die core power networks using package level vector network analyzer (VNA) S21 measurements. The technique uses the two-port self-impedance measurement concept for low impedance power distribution networks (PDN) (Novak, 2000). It is validated mathematically through network analysis and makes use of an auxiliary test fixture to de-embed the chip...
Thin dielectrics with a high dielectric constant are very attractive for improving the decoupling performance of digital and mixed-signal systems. Accurate estimation of the dielectric constant and the loss tangent is important to calculate the impedance profile or the cavity resonances. Extracting the electrical properties of thin and high-K dielectrics is difficult using conventional methods such...
A method to measure the impedance Z(f) of a chip/package/board power supply system using pseudo-impulse current is described. This method can be easily applied to the digital systems with synchronous clocking systems. A PowerPC based microprocessor power supply system is used as an example to show the effectiveness of the method
Understanding the AC current flowing through BGA package pins is critical to create accurate models of the power distribution network. We show that these currents can be experimentally measured by inserting small induction loops next to the vias carrying the pin currents. Small induction loops were constructed which gave a measurement upper cutoff frequency of 2 GHz, and a sensitivity of about 0.14...
This paper presents a new systematic approach to the design of the power distribution networks containing EBG structures. A stepped impedance filter layout is used to design the EBG unit cell. The final design is optimized in a few seconds by using a 2D analytical technique to predict the EBG band diagram
Electromagnetic band gap (EBG) synthesizer using genetic algorithm has been applied for noise suppression in mixed signal system applications. EBGs have been successfully synthesized, designed, simulated, fabricated, and measured for noise isolation in mixed signal systems
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.