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The increased component density of a 3D system-on-package (SOP) exacerbates the thermal hotspot problem. A popular choice to mitigate the thermal issues is thermal vias (t-vias) that are used to establish thermal paths from the core of an SOP package to the heat sinks. Another major problem with SOP integration is the power supply noise coupling among various mixed signal components constituting the...
Closed form analytical solutions for the stresses in the IC package-to-PCB interconnection when subjected to JEDEC STD board level drop test have been developed and validated. The solutions offer useful insights into the mechanics of board level interconnection in drop impact and have been used to (i) investigate the degrees of symmetry of PCB flexing on the interconnection stress; (ii) perform parametric...
High-K inorganic materials generally show high loss or high TCC or both, making them unsuitable for RF capacitor applications where high Q, tolerance and thermal stability are critical. Most polymers do not have the required total set of attributes, making it extremely challenging to integrate high-performance RF thin film capacitors in organic packages and boards. In this paper, we demonstrate a...
The role of underfills is expanding from preserving solder joint reliability to also protecting fragile low-k chip dielectric layers. Traditionally, solder joints required stiff and rigid underfills. Today, low-k layers require more compliant underfill properties. Further complexity comes from the migration to Pb-free solders and changes in chip carrier materials. The myriad of candidates prohibits...
Reliability of the flip-chip plastic ball grid array (FC-PBGA) packages is highly dependent on the properties of the constituent components and the interface formed between them. The relative mechanical compliances and thermal mismatch between the silicon chip, the underfill material and the organic laminate substrate are particularly important to the design and performance the package. Strong coupling...
This paper reports on the development of a 3D interconnection process leading to the successful assembly of a five-layer 3-D 1 mm cube module. This proof of concept module demonstrates the capability for successful integration and interconnection of commercial off the shelf components to fabricate functional modules in 1 mm cube dimensions. It also demonstrates that use of established volume scale...
Low temperature co-fired ceramic (LTCC) technology is the preferred platform for integrating multi-layer capacitors due to excellent high frequency performance and low-loss dielectric properties. This letter describes an approach to perform modeling of multi-layer capacitors in LTCC technology. This hybrid approach combines both analytical modeling and numerical modeling to provide a scalable circuit...
To accurately evaluate interconnect net electrical properties of the tri-grid structure we need to model the wires and vias in this structure. Due to the high application frequencies and the non-TEM nature of the propagating mode in this structure, the use of full-wave electromagnetic tools is necessary. In this paper we describe the principles and results of three different modeling and simulation...
This paper presents voltage controlled oscillator (VCO) circuit employing MOS transistors intended for integrated transceiver, in which full compensation of process parameters variations can be obtained. This is realized by fitting on chip capacitance of LC resonator. This capacitance is used for tuning of resonant frequency. VCO output frequency is tuned by on-chip p /n-well junction varactors. The...
The benefits of copper (Cu) die-side bumps for flip chip application are well known and have been sought for more than a decade. However, the introduction of fragile low-k interlayer dielectrics (ILD's) into back end interconnect architectures have made integrating copper bumps challenging, i.e. low-k ILD cracking that often leads to partial or complete die failure. For the 65nm technology node, Intel...
When we encountered the bond pad metal peeling defects with low-K devices during wire bonding, we have a tendency to optimize 'bonding power', 'bonding force' and 'bond time' so far. But the effectiveness of improvement by evaluations was not so satisfactory as much as we have got with normal Si devices. So this brought us to assume existence of another important factors against the defects and initial...
With the increased use of Lead-free alloys in BGA packages and assemblies, new reliability issues have become critical. A common mode of failure during impact conditions for BGA assemblies is brittle failure at the interface between the BGA substrate pad and the bulk solder joint. However, the strength characteristics of these interfaces, which include an intermetallic compound (IMC) layer, are not...
For bidirectional optical link at 2.5 Gb/s, we designed and fabricated a driver-receiver combined CMOS transceiver in 0.18-mum technology, an optical connector, and an optical PCB. The CMOS transceiver provides both transmitting and receiving modes of operation on a single chip, showing -3-dB bandwidths of 2.2 GHz and 2.4 GHz, and small-signal isolations of -28 dB and -40 dB between operating modes,...
As telecommunication equipment that supports high-level information networks is being made portable, the requirements for telecommunication equipment to be small and lightweight are becoming stricter. Thus, miniaturization of semiconductor devices is necessary, and wafer dicing and chip thinning technologies are important key technologies to achieve it. Wafers are thinned by mechanical in-feed grinding...
Underfill delamination jeopardy in flip chip organic packages is driven by shear and peeling interfacial stresses, which are directly impacted by underfill fillet geometry. Finite element analysis (FEA) models were used to analyze the effect of underfill height and width on interfacial stresses in a typical organic flip chip package configuration. Peeling and shearing stresses were computed for a...
A semiconductor diamond-shaped ring laser was fabricated and packaged for further test and analysis as an element in digital photonic logic. The optical characteristics of the ring laser were quantified in order to design a prototype package. The mode field was found to be quasi-circular. Based on the mode field of the laser, coupling curves were calculated and Corning OptiFocustrade lensed fiber...
Let us have a look at the main spheres for silicon chips: The processors you find in your PCs, memory-chips used in nearly every electronic module, the power-devices your car is full of and the smart-labels found in access-cards, tickets and labeling applications which make our daily life easier. For each of these applications the chips are going thin. What is the driving force of this development,...
We have developed a high-density wiring interposer for 10-Gbps signal propagation using a photosensitive polyimide. We optimized the basic properties of the photosensitive polyimide film for the fabrication of the interposer. We experimentally confirmed that the high-density wiring interposer could be fabricated using the optimized polyimide and gold multilayered structure. Fine metal wirings were...
Cooling hot-spots with high heat flux (e.g., >1000W/cm2 ) is becoming one of the most important technical challenge facing today's IC industry. More aggressive thermal solutions, than would be required for uniform heating, are highly desired. Solid state thermoelectric coolers (TECs) have received recent attention for hot-spot thermal management. However, present day TECs typically have cooling...
There is increasing interest in the use of conductive polymeric adhesives as a replacement for soldering technology in electronic packaging applications. Relatively low cost, lower toxicity, reworkability and ease of processing make them an attractive alternative. To date, however, most conductive adhesives have certain critical limitations that inhibit their utility in many applications. We report...
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