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Technology scaling results in reduction of the lateral and vertical dimensions of transistors. The supply voltage (VDD) is scaled down to reduce power dissipation and to maintain device reliability (avoid oxide breakdown). The threshold voltage (Vt) is proportionally scaled down in order to maintain the performance. However, narrow oxide thickness and low Vt result in significant rise in gate leakage...
With the increasing complexity of VLSI circuits and systems, their testing is becoming increasingly complex and time consuming. Apart from affecting the design turn-around time, it poses severe challenges to the test engineers in terms of meeting the power-budget and temperature limit of the chip. Power consumption during test is often much higher than in normal mode of operation. Increasing temperature...
For high end design, delay test becomes increasingly important. The paper proposes a technique to synthesize fully delay testable circuit without any additional control input. Our proposal is based on covering each ROBDD node by Invert-And-Or elements. We have shown that the generated circuit is fully testable either by robust tests or by validatable non-robust tests.
Data conversion operations are important and essential part of floating point units in a processor and typical instructions include conversion between various precisions, integer to floating point and vice versa, floating point to fixed point and vice versa etc. Besides few processors have instructions to round and truncate data, sign injections, move data between co-processors registers and general...
The paper addresses an attempt to perform dynamic timing simulations of complex mixed signal IP's. The targeted IP is a memory and uses its behavioural model; the idea spans from checking the presence of IO Path delays and timing checks viz. setup, hold, recovery, removal, width etc, and validating the impact on the IP behaviour. The methodology is developed and validated on UVM semantics; the eco-system...
There are two main directions in the development of modern microprocessor architectures used for System on Chip: low Power consumption and high performance. The paper presents the method for enhancing LEON3 processor IP core with superscalar ability for high-performance and low-power systems. As compared to the original LEON3 IP core, the proposed super scalar design executes is up to two instructions...
With the growing complexity of electronics circuits, one of the most critical task for a circuit designer is to design a suitable power distribution network for the desired functioning of electronic circuits. This is accomplished by analyzing power distribution network so that hotspots (lower supply voltages that cause excessive voltage drop) on power rails can be determined efficiently. Usually the...
Performance and reliability of nanoscale memory and logic devices is determined by few electron-phenomena. In this context, the organic molecules may offer some advantages for future memory applications. Since, a molecule is the smallest component whose electrical properties can be engineered, it can be argued that the ultimate integrated circuit will be constructed at the molecular level. This fact...
In this paper we address the problem of generating large combinational circuits with good fan in and fanout distribution, high Rent factor and large number of reconvergent gates. Such circuits are in great demand in testing various circuit related algorithms as bench mark circuits or networks. Generation of such circuits is conjectured to be NP Hard problem and available tools are mostly proprietary...
With increasing power demands in modern SoCs, macros are designed to operate in multiple low power modes depending upon the voltage value of each supply. Power Aware simulations have been recently in use for simulating and verifying these low power features at the RTL level. The supplies inside PA models of IOs are modeled as ‘reg’ type and can only carry logic values 0/1. These logic values does...
Throughput-sensitive server workloads are expected to handle voluminous independent and concurrent transactions that require careful designing of an on chip interconnect. State of the art applications take in a very high and even unbounded working sets with concurrent data. It demands for suitable architectural changes for on chip interconnect to maintain the performance of concurrent applications...
Floating point multiply-accumulate (FPMAC) block is a key unit determining the frequency, power and area of microprocessors. FPMAC unit is used in engineering and scientific applications. In this work we have proposed a novel FPMAC architecture which focuses on optimal computations to make it the fastest FPMAC as of today in literature. Innovations to create a novel Single Precision Dual Multiplier...
In this extended abstract, we propose a pipelined parallel architecture for face detection that is appropriate for implementation on a multicore environment. The architecture comprises of modules for video frame acquisition, skin pixel detection, binarization, morphological operations and connected component analysis operating in sequence on an image frame. Successive lines of a frame are processed...
The microfabrication technology has had a chequered history of over 50 years in the field of microelectronics. Aggressive miniaturization of microelectronic devices has resulted in faster logic circuits; & and it has also reduced their power requirements. MOSFET device dimensions have already entered the sub-100 nanometer regime. The same successful principles of microfabrication were applied...
Radiation Hardened By Design (RHBD) combinational circuits/primitive gates using 0.18um CMOS Technology is developed for Space application with help of Cogenda TCAD software suite. The proposed combinational cells are investigated for radiation simulation using three dimensional (3D) device structure. Single Event Transient (SET) caused by proton, α particle and heavy ions like C, Ar and Kr is observed...
With the widespread use of applications like internet banking, secured communication, emails, etc. information security is important concern. Security of information depends on implementation of cryptographic algorithm and its complexity to solve in reverse direction. However, with the use of current high speed computational resources it is possible to carry out brute-force attack and various other...
QCA (Quantum-dot Cellular Automata) is the promising future nanotechnology for computing. In QCA, the cells must be aligned properly at nano scales for proper functioning. Defects may occur in synthesis and deposition phase. So the defect analyses and testing cannot be ignored. This paper presents a survey on QCA basics, defect characterization and various testing aspects of QCA.
Register File (RF), Static Random Access Memory (SRAM) and Read Only Memory (ROM) arrays on SoCs comprise over 50% area and consumes substantial power on die. The On die ROM usage is increasing as there is an increased focus on IOTs, multi-core microprocessor for notebooks, 2-in-1s and mobile applications. Achieving high performance at low power specification need considerable innovation. Use of High...
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