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With the increasing complexity of VLSI circuits and systems, their testing is becoming increasingly complex and time consuming. Apart from affecting the design turn-around time, it poses severe challenges to the test engineers in terms of meeting the power-budget and temperature limit of the chip. Power consumption during test is often much higher than in normal mode of operation. Increasing temperature...
With the widespread use of applications like internet banking, secured communication, emails, etc. information security is important concern. Security of information depends on implementation of cryptographic algorithm and its complexity to solve in reverse direction. However, with the use of current high speed computational resources it is possible to carry out brute-force attack and various other...
Semi-Conductor Laboratory (SCL) Fab. has been upgraded to 8" wafer fab to support 180 nm CMOS process made available by M/s. Tower Semiconductor Ltd, Israel. This tutorial describes SCL foundry process features and capabilities. The tutorial will cover SCL Fab base line technology features, analog process modules, digital standard cell library for core and I/Os and memory modules. End to end...
Due to the shrinking transistor sizes, the density of ICs roughly doubles every year as predicted by Moore's law. These advancements in the VLSI integration densities towards the nano scale era, witnessed a paradigm shift from computation centric designs to communication centric designs incorporating very large number of simple cores. Plenty of traditional interconnect schemes like point to point,...
The performance of multiplication in terms of speed and power is crucial for most of the Digital Signal Processing (DSP) applications. Many researchers have come up with various multipliers such as array, Booth, carry save, Wallace tree and modified Booth multipliers. However, for the present day applications Vedic multipliers based on Vedic Mathematics are presently under focus due to their high...
Traditionally BIST is most widely used testing methodology because of its online and at speed testing capability. The conventional BIST suffers from hardware overhead due to the presence of on-chip test blocks such as TPG, MISR, ROM and ORA. In this paper a low hardware cost BIST is proposed, which eliminates the requirement of external TPG by reconfiguring the first flops of scan chains as TPG and...
The emerging computational complexities arises the need of fast multiplication unit. The importance of multiplication in various applications necessitates improvement in its design so as to obtain the multiplication result efficiently. Multiplication operation can be improved by reducing the number of partial products to be added and by enhancing the adder unit for obtaining sum. The number of partial...
The emerging computational complexities arises the need of fast multiplication unit. The importance of multiplication in various applications necessitates improvement in its design so as to obtain the multiplication result efficiently. Multiplication operation can be improved by reducing the number of partial products to be added and by enhancing the adder unit for obtaining sum. The number of partial...
The testing power is the biggest concern in modern VLSI chip testing as the testing power is very greater than the functional power which affects the reliability of the chip. In this paper low test power architecture is proposed which loads the pattern in one scan chain serially and the rest scan chains are loaded parallel by the serial scan chain one after the other. The proposed technique is very...
Increase in design complication for current and future era of microelectronics technologies and mechanisms used for data transmission leads to an increased sensitivity to bit-flip errors. As we know, multiple cores are built in a single system on chip (SoC) and to test that SoC, test vectors are transferred from automatic test equipment (ATE) via serial communication link. Now if there is a defect...
The guard zone G (of width r) of a simple polygon P is a closed region consisting of a set of straight line segments and circular arcs (of radius r) bounding the said polygon such that there exists no pair of points p (on the boundary of P) and q (on the boundary of G) having their Euclidean distance d(p, q) less than the specified value r. In this paper we have designed a cost-optimal (parallel)...
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