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With the advancement in technologies, data storage has become crucial for low power applications. Static random access memory (SRAM) is popular for its fast access of data but it is prone to high power dissipation. Adiabatic logic is one of the techniques which have proven to reduce the energy consumed by the circuit per operation. A novel adiabatic SRAM cell has been proposed in this paper. The proposed...
High performance SOC contains considerable amount of SRAM memory occupying more than 60% of total SOC area. In CMOS process scaling down of feature size enables higher density and lower cost but high density array has significant impact on manufacturing yield and performance parameters of conventional 6T SRAM cell. In this paper we have presented an alternate area compact 5 transistor portless SRAM...
The present work analyses 6T, 8T and 10T SRAM cell on the basis of the Data Retention Voltage (DRV) and its variation with temperature and sizing ratios. The reduction of power supply, for reduced power dissipation, is carried out in this paper. In this paper, DRV of a 6T, 8T and 10T SRAM was measured using Cadence tools at 45nm technology. The DRV of 6T SRAM cell simulated is compared with the DRV...
Cell stability with efficient operation are the two major concerns towards the design of SRAM bit cells in sub nanometer CMOS technologies. Supply scaling, intra-die parameter variations are some of the major factors governing the cell stability and controllability. This paper analyses the different stability criteria and the effect of various assist techniques in designing a SRAM cell for high speed...
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