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Throughput-sensitive server workloads are expected to handle voluminous independent and concurrent transactions that require careful designing of an on chip interconnect. State of the art applications take in a very high and even unbounded working sets with concurrent data. It demands for suitable architectural changes for on chip interconnect to maintain the performance of concurrent applications...
In embedded system-on-a-chip (SoC) applications, the demand for integration of heterogenous processors on a single chip is increasing. It adds complexity in maintaining coherency in data caches of the heterogeneous processors implementing different coherence protocols. Therefore, the task of coherence verification also becomes non-trivial for such a system. This work proposes an effective solution...
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