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The paper addresses an attempt to perform dynamic timing simulations of complex mixed signal IP's. The targeted IP is a memory and uses its behavioural model; the idea spans from checking the presence of IO Path delays and timing checks viz. setup, hold, recovery, removal, width etc, and validating the impact on the IP behaviour. The methodology is developed and validated on UVM semantics; the eco-system...
With increasing power demands in modern SoCs, macros are designed to operate in multiple low power modes depending upon the voltage value of each supply. Power Aware simulations have been recently in use for simulating and verifying these low power features at the RTL level. The supplies inside PA models of IOs are modeled as ‘reg’ type and can only carry logic values 0/1. These logic values does...
Throughput-sensitive server workloads are expected to handle voluminous independent and concurrent transactions that require careful designing of an on chip interconnect. State of the art applications take in a very high and even unbounded working sets with concurrent data. It demands for suitable architectural changes for on chip interconnect to maintain the performance of concurrent applications...
Register File (RF), Static Random Access Memory (SRAM) and Read Only Memory (ROM) arrays on SoCs comprise over 50% area and consumes substantial power on die. The On die ROM usage is increasing as there is an increased focus on IOTs, multi-core microprocessor for notebooks, 2-in-1s and mobile applications. Achieving high performance at low power specification need considerable innovation. Use of High...
Due to the shrinking transistor sizes, the density of ICs roughly doubles every year as predicted by Moore's law. These advancements in the VLSI integration densities towards the nano scale era, witnessed a paradigm shift from computation centric designs to communication centric designs incorporating very large number of simple cores. Plenty of traditional interconnect schemes like point to point,...
A test circuit for measuring the de-assertion threshold of a Power-on-Reset (POR) circuit is presented. With the help of the test circuit, POR de-assertion voltage can be measured without requiring a dedicated analog pad or a supply voltage higher than the POR supply voltage. The test circuit does not impact the normal mode of operation of POR and the area and power overhead due to the addition of...
High performance SOC contains considerable amount of SRAM memory occupying more than 60% of total SOC area. In CMOS process scaling down of feature size enables higher density and lower cost but high density array has significant impact on manufacturing yield and performance parameters of conventional 6T SRAM cell. In this paper we have presented an alternate area compact 5 transistor portless SRAM...
State of the art automotive microcontrollers (MCUs) implementing complex system-on-chip (SoC) architectures requires often additional functional patterns to achieve high degree of reliability. Functional pattern family includes test patterns checking internal device functionality under nominal condition. The development of these patterns is required to augment structural tests to achieve high test...
This paper proposes a new sensor circuit to monitor on-chip frequency temperature changes in VLSI circuits. The proposed circuit exploits the temperature dependency of current/voltage of metal-oxide-semiconductor field effect transistor. The variation of current/voltage in the temperature sensor circuit with respect to temperature is subjected to a ring oscillator which provides the relative frequency...
Hardware IP design verification is performed using exhaustive random stimuli, while incorporating a coverage driven flow. On the other hand, system-on-chip (SoC) verification methodologies, sometimes, use a directed C-based verification approach to validate the functionality of the design. There is no significant randomization exercised in this process. Reuse of IP testbench components for SoC verification...
Embedded processors with cache memories are used to improve the overall performance of the system. To maintain a trade-off between cache size costs vs. performance, it is required to avoid oversize cache. A quick estimation of cache size at the early stage of design cycle may help the system architect to plan the available chip area among processing core, cache memory, register file and other system...
Rapid growth in the cache sizes of Chip Multiprocessors (CMPs) to support high performance applications will lead to increase in wire-delays and unexpected access latencies. NUCA architectures help in managing the capacity and access time for such larger cache designs. Static NUCA (S-NUCA) has a fixed address mapping policy whereas dynamic NUCA (D-NUCA) allows blocks to relocate nearer to the processing...
To maintain the ever increasing demand for compaction as well as performance, 3D ICs were introduced. They have some additional advantages over their 2D counterparts in various aspects like heterogeneous integration, higher frequency, lesser interconnect length and increased bandwidth. Testing of core-based dies in 3D-SOCs poses many new challenges. This paper describes an automated post-bond core-based...
In embedded system-on-a-chip (SoC) applications, the demand for integration of heterogenous processors on a single chip is increasing. It adds complexity in maintaining coherency in data caches of the heterogeneous processors implementing different coherence protocols. Therefore, the task of coherence verification also becomes non-trivial for such a system. This work proposes an effective solution...
Most of the chip-multiprocessors share a large sized last level cache(LLC) which is divided into multiple banks in NUCA based architectures. Recent study on LLC power consumption indicates that, LLC consumes principal amount of chip power. The LLC power consumption can be divided into two major parts: dynamic power and static power. Techniques have been proposed to reduce static power by powering...
With the entry into the embedded domain, security of SOC architectures has become an arena of importance. However, complexity and cost factors have forced us to outsource the VLSI design phases across the globe. Such sites may not be trusted and threat lies in the introduction of malicious intrusions at any stage of the design flow. Such malicious intrusions, also known as Hardware Trojan Horses (HTH)...
The size and complexity of system-on-chip (SoC) design is growing rapidly as more and more IPs/features/functions are put into single die to reduce overall system development cost. It significantly increases SoC verification challenges in recent time due to high degree of integration of complex IPs. In this paper we will be discussing different verification strategies in different areas of verification...
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