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Traditionally BIST is most widely used testing methodology because of its online and at speed testing capability. The conventional BIST suffers from hardware overhead due to the presence of on-chip test blocks such as TPG, MISR, ROM and ORA. In this paper a low hardware cost BIST is proposed, which eliminates the requirement of external TPG by reconfiguring the first flops of scan chains as TPG and...
The testing power is the biggest concern in modern VLSI chip testing as the testing power is very greater than the functional power which affects the reliability of the chip. In this paper low test power architecture is proposed which loads the pattern in one scan chain serially and the rest scan chains are loaded parallel by the serial scan chain one after the other. The proposed technique is very...
Temperature of a block (a region in the chip) depends on both heat generation (caused by power consumption) and heat dissipation among neighbors. Power aware test solutions targeting low power consumption during testing, may not produce an acceptable thermal aware solution. In this paper, a particle swarm optimization (PSO) based test pattern generation strategy has been proposed for BIST environment...
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