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A fully integrated low power LNA is implemented using 65-nm RF CMOS technology for 2.14-GHz band. By taking the advantage of higher transition frequency of recent technologies, transistors are biased in the moderate inversion region and this permitted scaling down the supply voltage to 0.7 V. Further, the exploration of design spaces from strong to weak inversion led to the development of a low power...
To maintain the ever increasing demand for compaction as well as performance, 3D ICs were introduced. They have some additional advantages over their 2D counterparts in various aspects like heterogeneous integration, higher frequency, lesser interconnect length and increased bandwidth. Testing of core-based dies in 3D-SOCs poses many new challenges. This paper describes an automated post-bond core-based...
Vibrational energy harvesters (VEH) are increasingly becoming the favourite approach towards making self sustained low power systems. However, obtaining frequencies close to those of ambient vibrations has been a challenge. In the current work we have proposed a novel design of the piezoelectric-VEH (P-VEH) consisting of a micro-machined thick silicon proof mass suspended with quad-beams carved out...
Advantage of 3D ICs is that it has reduced wire-length and greater performance compared to conventional 2D ICs. It is important that a 3D placement tool obtains improved wirelength over 2D placement. In this paper we present the implementation of our 3D placement tool. Our work is based on analytical framework, where we solve nonlinear equations. Placement problem is modeled as quadratic penalty for...
Digital multiplier and squarer circuits are indispensable in Digital signal processing and cryptography. In many mathematical computations, squaring and cubing are frequently used. Generally the multiplier is used in computing square. Using multiplier, the partial products of the squarer are generated which are added to achieve the final output. But the implementation of squaring has the advantage...
Power Optimal logic depth per pipeline stage has been explored in several papers in the literature. Simulation results on circuit models with inverters have shown that a logic depth per pipeline stage of 6 to 8 FO4 results in optimal power designs and can save good amount of power compared to a logic depth of 24 F04. In this paper we study power and logic depth trade off on ISCAS-85 benchmark circuits,...
In this work, novel layouts of a 4:1 CMOS transmission gate multiplexer are presented. The proposed layouts are realized by following the design rules for 45 nm and 90 nm CMOS processes, with a supply voltage of 1.2 V. Both layouts are designed using two different routing strategies — using only one metal layer, and using two metal layers. The power dissipation and area are noted and compared in all...
An essential job of combinational logic synthesis is to optimize the area and power of the synthesized circuit. Two-level and three level logic minimization for area and power are the well researched areas. Recently temperature minimization has been emerged as the new dimension in logic synthesis. Thermal aware AND-OR-XOR network realization is considered in this research work. In this paper attention...
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