Serwis Infona wykorzystuje pliki cookies (ciasteczka). Są to wartości tekstowe, zapamiętywane przez przeglądarkę na urządzeniu użytkownika. Nasz serwis ma dostęp do tych wartości oraz wykorzystuje je do zapamiętania danych dotyczących użytkownika, takich jak np. ustawienia (typu widok ekranu, wybór języka interfejsu), zapamiętanie zalogowania. Korzystanie z serwisu Infona oznacza zgodę na zapis informacji i ich wykorzystanie dla celów korzytania z serwisu. Więcej informacji można znaleźć w Polityce prywatności oraz Regulaminie serwisu. Zamknięcie tego okienka potwierdza zapoznanie się z informacją o plikach cookies, akceptację polityki prywatności i regulaminu oraz sposobu wykorzystywania plików cookies w serwisie. Możesz zmienić ustawienia obsługi cookies w swojej przeglądarce.
The simulated cross section of vertical gate RF SOI LIGBT with TCAD ATHENA is illustrated in Fig. 8 by using the constrains of advanced SOI CMOS VLSI technologies, which demonstrates that the proposed device cell structure is feasible in technology with advanced SOI CMOS VLSI technologies. The primarily simulated current-voltage characteristics of RF SOI LDMOS/LIGBT cell does not latch-up at VGS=2...
In this paper, we have revealed major implant process that improves for the mismatch on the 65nm CMOS technology. Two more effective experiments are been presented, i.e. threshold implant energy and species. As a result, the impact of threshold implant process on the matching characteristic has been demonstrated. In addition, the threshold implant of higher energy and heavy species are two unusual...
In this paper, a novel 3-input AND gate with one clock zone and area same as one AND gate, is proposed. The idea uses two-layer majority gate. A bias is applied from the top of the majority. To implement an AND/OR gate, the bias should be "0" or "1" respectively. The bias changes the equilibrium point of the polarization.
In recent years, researchers have been interested to implement computational circuits by nanotechnology since it has many attractive advantages. Quantum-dot cellular automata (QCA) is one of the most attractive and profitable nanotechnology that was first proposed in 1993. A design of ring counter was introduced in 2008 for the first time. After that, a 4-bit counter based on ring counter, was proposed...
A study of the substrate current was presented for a PD-SOI MOSFET under forward substrate bias. The substrate current is almost independent of the gate voltage and is dominated by the SSJ diffusion current for a bias above ~0.6V. BSIMSOI agrees only qualitatively with SENTAURUS simulations, and the model for the SSJ diffusion current must be reviewed in order to quantify accurately the substrate...
The gate C-V characteristics of MOS device with ultrathin gate dielectrics and different types of non-uniform substrate doping profile with quantum mechanics (QM) treatment is presented. Self-consistent solution of Schrodinger's and Poisson's equations with wave function penetration are used to determine the MOS electrostatics, and results show that at low-frequency the C-V characteristic curves depend...
EEPROM cell with n-well and MIM capacitor is proposed and fabrication is done by using the 0.18??m standard CMOS process. Single polysilicon EEPROM cell applies the stacked metal-insulator-metal (MIM) or n-well capacitor to increase a memory capacity. Although MIM capacitor cell shows a good device performance, it requires a large device-size. N-well control gate cell has an inherent high junction...
In this paper, the designed transconductance-match biosensor systems for differential readout electronics were investigated. Through optimizing the composition of membranes of REFETs, the transconductance match for biosensor and REFET pairs was determined. With the simple readout electronics requirements, such pairs can be easily integrated into miniature onchip scale, which are also capable of performing...
A gate-last MOSFET has been suggested for 32 nm node CMOSFET, where the integration of a high-k gate dielectric and a metal gate electrode becomes essential to meet the transistor performance requirement. The gate-last MOSFET has been demonstrated as an effective integration scheme to avoid thermal instability and workfunction mismatch issues. Even though feasibility of such gate structure for the...
We focus in this work on threshold logic gates (TLQ) implemented using double-gate (DG) MOSFETs. The proposed TLQ's can be programmed dynamically via secondary (back) gate using the same bias conditions as the primary (front) gate. Moreover, they can realize universal threshold logic functions, which comprise Boolean operations as a subset.
This paper introduces a new SiGe stepped gate (SSG) thin film SOI LDMOS for enhanced performance. The proposed device eliminates the premature breakdown of the device due to floating body effects, which is one major problem of the thin film SOI LDMOS. The most common technique used to eliminate the floating body effects in SOI power device is the source tied body contact. Though this technique is...
Lateral channel engineering utilizing halo-pocket implant surrounding drain and source regions is effective in suppressing short channel effects. However, the reported model cannot be extended further to the pocket implantation, where inhomogeneity along the channel is the main cause for the reverse short channel effect (RSCE). A strong reverse short channel effect suppresses the short channel effect...
Capacitance-voltage (C-V) characteristics of triple-gate (TG) and double gate (DG) silicon-on-insulator (SOI) FinFETs having sub 10 nm dimensions are obtained by self consistent method using coupled Schro??dinger-Poisson solver taking into account quantum mechanical effects. Though self-consistent simulation to determine current and short channel effects in these devices has been reported in recent...
Carbon nanotube (CNT) is one of the front line candidates for a possible replacement. Remarkable electronic and mechanical properties of CNTs make them promising building blocks for future nanoelectronics. Failure to develop room-temperature multiwalled (MW) carbon nanotube field-effect transistors (CNTFETs) because of large radii corresponding to small band gap (~ few KT) encouraged researchers to...
In this work, we investigated effects of high pressure hydrogen annealing (HPHA) to improve the device performance of Si NW MOSFET devices with multi channels on SOI wafer using top down method which may be more compatible to CMOS process.
SiGe buried channel with different Ge contents and various thicknesses of Si-cap layer on operation characteristics of charge-trapping (CT) flash devices were studied in this work. The programming and erasing speeds of CT flash devices are significantly improved by employing SiGe buried channel. The retention properties of CT flash devices are satisfactory with suitable Ge content in SiGe buried channel...
Podaj zakres dat dla filtrowania wyświetlonych wyników. Możesz podać datę początkową, końcową lub obie daty. Daty możesz wpisać ręcznie lub wybrać za pomocą kalendarza.