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This paper presents an innovative way to design competitive ESD protection networks in advanced FDSOI CMOS technology thanks to Hybrid Bulk co-integration. An optimal placement of elementary ESD devices is discussed and their ESD performances are compared. The advantage of the co-integration is also demonstrated on an ESD network design development.
In this paper, we propose a new hetero-material stepped gate (HSG) SOI LDMOS in which the gate is divided into three sections - an n+ gate sandwiched between two p+ gates and the gate oxide thickness increases from source to drain. This new device structure improves the inversion layer charge density in the channel, results in uniform electric field distribution in the drift region and reduces the...
This paper introduces a new SiGe stepped gate (SSG) thin film SOI LDMOS for enhanced performance. The proposed device eliminates the premature breakdown of the device due to floating body effects, which is one major problem of the thin film SOI LDMOS. The most common technique used to eliminate the floating body effects in SOI power device is the source tied body contact. Though this technique is...
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